[RISCV] Relax codegen predicates for HINT-based instructions (#179872)

Following the assembler/disassembler changes in #178609, this patch also
relaxes the codegen predicates for HINT-based instructions. Since these
instructions use encodings that are architecturally guaranteed not to
trap, the compiler can safely generate them regardless of extension
availability.

Changes:
- int_riscv_pause: Remove HasStdExtZihintpause predicate. The pause
intrinsic now generates the FENCE hint encoding unconditionally.
- NTL hints: Remove hasStdExtZihintntl() check in emitNTLHint().
Non-temporal locality hints are now emitted for all nontemporal memory
operations.

Author: kito-cheng

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

@@ -273,18 +273,19 @@ bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
 // instructions) auto-generated.
 #include "RISCVGenMCPseudoLowering.inc"
 
-// If the target supports Zihintntl and the instruction has a nontemporal
-// MachineMemOperand, emit an NTLH hint instruction before it.
+// If the instruction has a nontemporal MachineMemOperand, emit an NTL hint
+// instruction before it. NTL hints are always safe to emit since they use
+// HINT encodings that are guaranteed not to trap
+// (riscv-non-isa/riscv-elf-psabi-doc#474).
 void RISCVAsmPrinter::emitNTLHint(const MachineInstr *MI) {
-  if (!STI->hasStdExtZihintntl())
+  if (!STI->getInstrInfo()->requiresNTLHint(*MI))
     return;
 
-  if (MI->memoperands_empty())
-    return;
+  assert(!MI->memoperands_empty());
 
   MachineMemOperand *MMO = *(MI->memoperands_begin());
-  if (!MMO->isNonTemporal())
-    return;
+
+  assert(MMO->isNonTemporal());
 
   unsigned NontemporalMode = 0;
   if (MMO->getFlags() & MONontemporalBit0)

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -3061,6 +3061,11 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     return;
   }
   case ISD::PREFETCH:
+    // MIPS's prefetch instruction already encodes the hint within the
+    // instruction itself, so no extra NTL hint is needed.
+    if (Subtarget->hasVendorXMIPSCBOP())
+      break;
+
     unsigned Locality = Node->getConstantOperandVal(3);
     if (Locality > 2)
       break;

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -1994,16 +1994,13 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
                               *MF.getTarget().getMCAsmInfo());
   }
 
-  if (!MI.memoperands_empty()) {
-    MachineMemOperand *MMO = *(MI.memoperands_begin());
-    if (STI.hasStdExtZihintntl() && MMO->isNonTemporal()) {
-      if (STI.hasStdExtZca()) {
-        if (isCompressibleInst(MI, STI))
-          return 4; // c.ntl.all + c.load/c.store
-        return 6;   // c.ntl.all + load/store
-      }
-      return 8; // ntl.all + load/store
+  if (requiresNTLHint(MI)) {
+    if (STI.hasStdExtZca()) {
+      if (isCompressibleInst(MI, STI))
+        return 4; // c.ntl.all + c.load/c.store
+      return 6;   // c.ntl.all + load/store
     }
+    return 8; // ntl.all + load/store
   }
 
   if (Opcode == TargetOpcode::BUNDLE)
@@ -5326,3 +5323,14 @@ bool RISCVInstrInfo::isVRegCopy(const MachineInstr *MI, unsigned LMul) const {
       RISCVVType::decodeVLMUL(RISCVRI::getLMul(RC->TSFlags));
   return (!RCFractional && LMul == RCLMul) || (RCFractional && LMul == 1);
 }
+
+bool RISCVInstrInfo::requiresNTLHint(const MachineInstr &MI) const {
+  if (MI.memoperands_empty())
+    return false;
+
+  MachineMemOperand *MMO = *(MI.memoperands_begin());
+  if (!MMO->isNonTemporal())
+    return false;
+
+  return true;
+}

llvm/lib/Target/RISCV/RISCVInstrInfo.h

@@ -330,6 +330,9 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
   /// or any kind of vector registers when \p LMul is zero.
   bool isVRegCopy(const MachineInstr *MI, unsigned LMul = 0) const;
 
+  /// Return true if the instruction requires an NTL hint to be emitted.
+  bool requiresNTLHint(const MachineInstr &MI) const;
+
   /// Return true if pairing the given load or store may be paired with another.
   static bool isPairableLdStInstOpc(unsigned Opc);
 

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -2316,8 +2316,8 @@ def : Pat<(i64 (add GPR:$rs1, negImm:$rs2)), (SUB GPR:$rs1, negImm:$rs2)>;
 // Zihintpause
 //===----------------------------------------------------------------------===//
 
-// Zihintpause
-let Predicates = [HasStdExtZihintpause] in
+// int_riscv_pause is always available since pause is a HINT encoding that is
+// guaranteed not to trap (riscv-non-isa/riscv-elf-psabi-doc#474).
 def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>;
 
 //===----------------------------------------------------------------------===//