[RISCV] Add an implementation of findRepresentativeClass to assign i32 to GPRRegClass for RV64.

This is an alternative fix for #81192. This allows the SelectionDAG
scheduler to be able to find a register class for i32 on RV64. The
default implementation of findRepresentativeClass only works for
legal types which i32 is not for RV64.

I wanted to remove i32 from the GPR register class to fix the issue,
but we need to be able to write some i32 patterns for GISel. And now
it looks like I need to add i16 to GPR. I had tried to use manual
instruction selection for some cases in GISel in #116111, but I got
some feedback recommending the use of patterns.

I did some investigation of why tablegen uses i32 in output patterns
on RV64. It appears it comes down to ForceArbitraryInstResultType
that just picks a type for the output pattern when the isel pattern
isn't specific enough. I believe it picks the smallest type(lowested
numbered) to resolve the conflict.

Author: topperc

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -21996,6 +21996,24 @@ SDValue RISCVTargetLowering::expandIndirectJTBranch(const SDLoc &dl,
   return TargetLowering::expandIndirectJTBranch(dl, Value, Addr, JTI, DAG);
 }
 
+// Some types are listed in the GPR register class to support isel patterns for
+// GISel, but are not legal in SelectionDAG. This prevents the default
+// implementation from finding a register clss for them.
+std::pair<const TargetRegisterClass *, uint8_t>
+RISCVTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
+                                             MVT VT) const {
+  const TargetRegisterClass *RRC = nullptr;
+  uint8_t Cost = 1;
+  switch (VT.SimpleTy) {
+  default:
+    return TargetLowering::findRepresentativeClass(TRI, VT);
+  case MVT::i8: case MVT::i16: case MVT::i32:
+    RRC = &RISCV::GPRRegClass;
+    break;
+  }
+  return std::make_pair(RRC, Cost);
+}
+
 namespace llvm::RISCVVIntrinsicsTable {
 
 #define GET_RISCVVIntrinsicsTable_IMPL

llvm/lib/Target/RISCV/RISCVISelLowering.h

@@ -1051,6 +1051,9 @@ class RISCVTargetLowering : public TargetLowering {
 
   SDValue emitFlushICache(SelectionDAG &DAG, SDValue InChain, SDValue Start,
                           SDValue End, SDValue Flags, SDLoc DL) const;
+
+  std::pair<const TargetRegisterClass *, uint8_t>
+  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override;
 };
 
 namespace RISCVVIntrinsicsTable {