Update ARMISelLowering.cpp

Author: AZero13

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -20144,15 +20144,30 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
   }
 }
 
+static bool isLegalLogicalImmediate(unsigned Imm, const ARMSubtarget *Subtarget) {
+  // Handle special cases first
+  if (!Subtarget->isThumb())
+    return ARM_AM::getSOImmVal(Imm) != -1;
+  if (Subtarget->isThumb2())
+    return ARM_AM::getT2SOImmVal(Imm) != -1;
+  // Thumb1 only has 8-bit unsigned immediate.
+  return Imm <= 255;
+}
+
 static bool optimizeLogicalImm(SDValue Op, unsigned Size, unsigned Imm,
                                const APInt &Demanded,
                                TargetLowering::TargetLoweringOpt &TLO,
-                               unsigned NewOpc) {
+                               unsigned NewOpc, const ARMSubtarget *Subtarget) {
   unsigned OldImm = Imm, NewImm, Enc;
   unsigned Mask = ~0U, OrigMask = Mask;
-
+  bool Invert = false;
+  
   // Return if the immediate is already all zeros, all ones, a bimm32.
-  if (Imm == 0 || Imm == Mask)
+  if (Imm == 0 || Imm == Mask || isLegalLogicalImmediate(Imm, Subtarget))
+    return false;
+  
+  // bic/orn/eon
+  if ((Op.getOpcode() == ISD::AND || (Subtarget->isThumb2() && Op.getOpcode() == ISD::OR)) && isLegalLogicalImmediate(~Imm, Subtarget))
     return false;
 
   unsigned EltSize = Size;
@@ -20228,8 +20243,7 @@ static bool optimizeLogicalImm(SDValue Op, unsigned Size, unsigned Imm,
     // Otherwise, create a machine node so that target independent DAG combine
     // doesn't undo this optimization.
   } else {
-    Enc = AArch64_AM::encodeLogicalImmediate(NewImm, Size);
-    SDValue EncConst = TLO.DAG.getTargetConstant(Enc, DL, VT);
+    SDValue EncConst = TLO.DAG.getTargetConstant(NewImm, DL, VT);
     New = SDValue(
         TLO.DAG.getMachineNode(NewOpc, DL, VT, Op.getOperand(0), EncConst), 0);
   }
@@ -20285,25 +20299,7 @@ bool ARMTargetLowering::targetShrinkDemandedConstant(
     return false;
 
   unsigned Imm = C->getZExtValue();
-
-  bool isLegalLogicalImmediate(unsigned Imm, const ARMSubtarget *Subtarget) {
-  // Handle special cases first
-  if (Imm == 0 || Imm == 0xFFFFFFFF)
-    return true;
-    
-  if (!Subtarget->isThumb()) {
-    // ARM mode: check shifter operand immediate
-    return ARM_AM::getSOImmVal(Imm) != -1;
-  } else if (Subtarget->isThumb2()) {
-    // Thumb2 mode: check T2 shifter operand immediate  
-    return ARM_AM::getT2SOImmVal(Imm) != -1;
-  } else {
-    // Thumb1 mode: very limited
-    return Imm <= 255 || ARM_AM::isThumbImmShiftedVal(Imm);
-  }
-}
-
-  return optimizeLogicalImm(Op, Size, Imm, DemandedBits, TLO, NewOpc);
+  return optimizeLogicalImm(Op, Size, Imm, DemandedBits, TLO, NewOpc, Subtarget);
 }
 
 bool ARMTargetLowering::SimplifyDemandedBitsForTargetNode(