fixed tablegen mis indexing arguments and finally able to run tests locally

Author: KungFuDonkey

clang/include/clang/Basic/Builtins.td

@@ -5039,7 +5039,7 @@ def HLSLWaveActiveAnyTrue : LangBuiltin<"HLSL_LANG"> {
 def HLSLWaveActiveBitOr : LangBuiltin<"HLSL_LANG"> {
   let Spellings = ["__builtin_hlsl_wave_active_bit_or"];
   let Attributes = [NoThrow, Const];
-  let Prototype = "void (...)";
+  let Prototype = "unsigned int (unsigned int)";
 }
 
 def HLSLWaveActiveCountBits : LangBuiltin<"HLSL_LANG"> {

clang/lib/CodeGen/CGHLSLBuiltins.cpp

@@ -835,8 +835,9 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID,
            "Intrinsic WaveActiveBitOr operand must have a unsigned integer representation");
 
     Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveActiveBitOrIntrinsic();
-    return EmitRuntimeCall(
-        Intrinsic::getOrInsertDeclaration(&CGM.getModule(), ID), {Op});
+    return EmitRuntimeCall(Intrinsic::getOrInsertDeclaration(
+                               &CGM.getModule(), ID, {Op->getType()}),
+                           ArrayRef{Op}, "hlsl.wave.active.bit.or");
   }
   case Builtin::BI__builtin_hlsl_wave_active_count_bits: {
     Value *OpExpr = EmitScalarExpr(E->getArg(0));

clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl

@@ -11,7 +11,7 @@
 // CHECK-LABEL: test_uint
 uint test_uint(uint expr) {
   // DXCHECK:  %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.i32([[TY]] %[[#]])
-  // SPVCHECK:  %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.i32([[TY]] %[[#]])
+  // SPVCHECK:  %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.i32([[TY]] %[[#]])
   // CHECK:  ret [[TY]] %[[RET]]
   return WaveActiveBitOr(expr);
 }
@@ -21,7 +21,7 @@ uint test_uint(uint expr) {
 // CHECK-LABEL: test_uint64_t
 uint64_t test_uint64_t(uint64_t expr) {
   // DXCHECK:  %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.i64([[TY]] %[[#]])
-  // SPVCHECK:  %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.i64([[TY]] %[[#]])
+  // SPVCHECK:  %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.i64([[TY]] %[[#]])
   // CHECK:  ret [[TY]] %[[RET]]
   return WaveActiveBitOr(expr);
 }

clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl

@@ -5,34 +5,17 @@ uint test_too_few_arg() {
   // expected-error@-1 {{too few arguments to function call, expected 1, have 0}}
 }
 
-uint2 test_too_many_arg(uint2 p0) {
+uint test_too_many_arg(uint p0) {
   return __builtin_hlsl_wave_active_bit_or(p0, p0);
   // expected-error@-1 {{too many arguments to function call, expected 1, have 2}}
 }
 
-uint test_expr_bool_type_check(bool p0) {
-  return __builtin_hlsl_wave_active_bit_or(p0);
-  // expected-error@-1 {{invalid operand of type 'bool'}}
-}
-
-uint test_expr_float_type_check(float p0) {
-  return __builtin_hlsl_wave_active_bit_or(p0);
-  // expected-error@-1 {{invalid operand of type 'float'}}
-}
-
-uint2 test_expr_bool_vec_type_check(bool2 p0) {
-  return __builtin_hlsl_wave_active_bit_or(p0);
-  // expected-error@-1 {{invalid operand of type 'bool2' (aka 'vector<bool, 2>')}}
-}
-
-uint2 test_expr_float_type_check(float2 p0) {
-  return __builtin_hlsl_wave_active_bit_or(p0);
-  // expected-error@-1 {{invalid operand of type 'float2' (aka 'vector<float, 2>')}}
-}
-
-struct S { float f; };
+struct Foo
+{
+  int a;
+};
 
-uint test_expr_struct_type_check(S p0) {
+uint test_type_check(Foo p0) {
   return __builtin_hlsl_wave_active_bit_or(p0);
-  // expected-error@-1 {{invalid operand of type 'S' where a scalar or vector is required}}
+  // expected-error@-1 {{no viable conversion from 'Foo' to 'unsigned int'}}
 }

llvm/include/llvm/IR/IntrinsicsDirectX.td

@@ -154,7 +154,7 @@ def int_dx_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i1
 def int_dx_wave_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
 def int_dx_wave_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
 def int_dx_wave_getlaneindex : DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrConvergent, IntrNoMem]>;
-def int_dx_wave_reduce_or : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrConvergent, IntrNoMem]>;
+def int_dx_wave_reduce_or : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
 def int_dx_wave_reduce_max : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
 def int_dx_wave_reduce_umax : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
 def int_dx_wave_reduce_min : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;

llvm/include/llvm/IR/IntrinsicsSPIRV.td

@@ -120,7 +120,7 @@ def int_spv_rsqrt : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty]
   def int_spv_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
   def int_spv_wave_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
   def int_spv_wave_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
-  def int_spv_wave_reduce_or : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrConvergent, IntrNoMem]>;
+  def int_spv_wave_reduce_or : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
   def int_spv_wave_reduce_umax : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
   def int_spv_wave_reduce_max : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
   def int_spv_wave_reduce_min : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;