We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
RISCVInstrInfoZfh.td
1 parent 1d0ee12 commit 49ab1d7Copy full SHA for 49ab1d7
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -75,7 +75,7 @@ def ZhinxminZdinxExt : ExtInfo<"_INX", "Zfinx",
75
?, ?, FPR32INX, FPR64INX, FPR16INX>;
76
def ZhinxZdinx32Ext : ExtInfo<"_IN32X", "ZdinxGPRPairRV32",
77
[HasStdExtZhinx, HasStdExtZdinx, IsRV32],
78
- ?, ?, FPR32INX, FPR64IN32X, FPR16INX >;
+ ?, ?, FPR32INX, FPR64IN32X, FPR16INX>;
79
def ZhinxminZdinx32Ext : ExtInfo<"_IN32X", "ZdinxGPRPairRV32",
80
[HasStdExtZhinxmin, HasStdExtZdinx, IsRV32],
81
?, ?, FPR32INX, FPR64IN32X, FPR16INX>;
0 commit comments