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[SDAG] zext/sext undef should produce an undef value as also.
1 parent b5137cd commit 49aba6e

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2 files changed

+20
-20
lines changed

2 files changed

+20
-20
lines changed

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6224,8 +6224,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
62246224
return getNode(OpOpcode, DL, VT, N1.getOperand(0), Flags);
62256225
}
62266226
if (OpOpcode == ISD::UNDEF)
6227-
// sext(undef) = 0, because the top bits will all be the same.
6228-
return getConstant(0, DL, VT);
6227+
// sext(undef) = undef in a conservative way, because not all of the bits
6228+
// are zero and there is no mechanism tracking the undef part.
6229+
return getUNDEF(VT);
62296230
break;
62306231
case ISD::ZERO_EXTEND:
62316232
assert(VT.isInteger() && N1.getValueType().isInteger() &&
@@ -6244,8 +6245,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
62446245
return getNode(ISD::ZERO_EXTEND, DL, VT, N1.getOperand(0), Flags);
62456246
}
62466247
if (OpOpcode == ISD::UNDEF)
6247-
// zext(undef) = 0, because the top bits will be zero.
6248-
return getConstant(0, DL, VT);
6248+
// zext(undef) = undef in a conservative way, because not all of the bits
6249+
// are zero and there is no mechanism tracking the undef part.
6250+
return getUNDEF(VT);
62496251

62506252
// Skip unnecessary zext_inreg pattern:
62516253
// (zext (trunc x)) -> x iff the upper bits are known zero.

llvm/test/CodeGen/X86/zext-sext.ll

Lines changed: 14 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -11,34 +11,32 @@ define void @func(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {
1111
; CHECK-LABEL: func:
1212
; CHECK: # %bb.0: # %entry
1313
; CHECK-NEXT: movslq (%rsi), %rax
14-
; CHECK-NEXT: movl $4, %r8d
15-
; CHECK-NEXT: subq %rax, %r8
14+
; CHECK-NEXT: movl $4, %esi
15+
; CHECK-NEXT: subq %rax, %rsi
1616
; CHECK-NEXT: movq (%rdx), %rax
1717
; CHECK-NEXT: movswl 8(%rdi), %edx
18-
; CHECK-NEXT: movswl (%rax,%r8,2), %eax
18+
; CHECK-NEXT: movswl (%rax,%rsi,2), %eax
1919
; CHECK-NEXT: imull %edx, %eax
2020
; CHECK-NEXT: addl $2138875574, %eax # imm = 0x7F7CA6B6
2121
; CHECK-NEXT: cmpl $2138875574, %eax # imm = 0x7F7CA6B6
2222
; CHECK-NEXT: setl %dl
2323
; CHECK-NEXT: cmpl $-8608074, %eax # imm = 0xFF7CA6B6
24-
; CHECK-NEXT: setge %r8b
25-
; CHECK-NEXT: andb %dl, %r8b
26-
; CHECK-NEXT: movzbl %r8b, %edx
27-
; CHECK-NEXT: movslq %eax, %r8
28-
; CHECK-NEXT: movq %r8, %r9
24+
; CHECK-NEXT: setge %sil
25+
; CHECK-NEXT: andb %dl, %sil
26+
; CHECK-NEXT: movzbl %sil, %edx
27+
; CHECK-NEXT: movslq %eax, %rsi
28+
; CHECK-NEXT: movq %rsi, %rdi
2929
; CHECK-NEXT: negl %edx
30-
; CHECK-NEXT: subq %rax, %r9
30+
; CHECK-NEXT: subq %rax, %rdi
3131
; CHECK-NEXT: xorl %eax, %eax
3232
; CHECK-NEXT: testl $-2, %edx
33-
; CHECK-NEXT: cmovneq %rax, %r9
34-
; CHECK-NEXT: testl %r8d, %r8d
35-
; CHECK-NEXT: cmovnsq %rax, %r9
33+
; CHECK-NEXT: cmovneq %rax, %rdi
34+
; CHECK-NEXT: testl %esi, %esi
35+
; CHECK-NEXT: cmovnsq %rax, %rdi
3636
; CHECK-NEXT: movq (%rcx), %rax
37-
; CHECK-NEXT: subq %r9, %r8
38-
; CHECK-NEXT: leaq -2138875574(%rax,%r8), %rax
37+
; CHECK-NEXT: subq %rdi, %rsi
38+
; CHECK-NEXT: leaq -2138875574(%rax,%rsi), %rax
3939
; CHECK-NEXT: movq %rax, (%rcx)
40-
; CHECK-NEXT: movl $0, (%rdi)
41-
; CHECK-NEXT: movl $0, (%rsi)
4240
; CHECK-NEXT: retq
4341
entry:
4442
%tmp103 = getelementptr inbounds [40 x i16], ptr %a, i64 0, i64 4

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