format

castigli · castigli · commit 49b7e6af37ac · 2025-10-08T16:31:19.000+02:00
diff --git a/mlir/test/Examples/NVGPU/tools/nvdsl.py b/mlir/test/Examples/NVGPU/tools/nvdsl.py
@@ -84,8 +84,7 @@ def arrive(self, txcount: int = 0, predicate=None):
                 self.mbar_group_op, txcount_op, self.id_op, predicate=predicate
             )
         else:
-            nvgpu.mbarrier_arrive(self.mbar_group_op, self.id_op
-            )
+            nvgpu.mbarrier_arrive(self.mbar_group_op, self.id_op)
 
     def try_wait(self, phase: bool = False, ticks: int = 10000000):
         ticks_op = const(ticks)
@@ -143,7 +142,9 @@ def create_descriptor(self, device_ptr):
             device_ptr,
         )
         self.tma_descriptor = nvgpu.TmaCreateDescriptorOp(
-            tma_descriptor_ty, device_unranked_memref, list(map(const, self.tma_box_shape))
+            tma_descriptor_ty,
+            device_unranked_memref,
+            list(map(const, self.tma_box_shape)),
         )
         return self.tma_descriptor.result
 

Original file line number	Diff line number	Diff line change
`@@ -84,8 +84,7 @@ def arrive(self, txcount: int = 0, predicate=None):`
`84`	`84`	`self.mbar_group_op, txcount_op, self.id_op, predicate=predicate`
`85`	`85`	`)`
`86`	`86`	`else:`
`87`		`- nvgpu.mbarrier_arrive(self.mbar_group_op, self.id_op`
`88`		`- )`
	`87`	`+ nvgpu.mbarrier_arrive(self.mbar_group_op, self.id_op)`
`89`	`88`
`90`	`89`	`def try_wait(self, phase: bool = False, ticks: int = 10000000):`
`91`	`90`	`ticks_op = const(ticks)`
`@@ -143,7 +142,9 @@ def create_descriptor(self, device_ptr):`
`143`	`142`	`device_ptr,`
`144`	`143`	`)`
`145`	`144`	`self.tma_descriptor = nvgpu.TmaCreateDescriptorOp(`
`146`		`- tma_descriptor_ty, device_unranked_memref, list(map(const, self.tma_box_shape))`
	`145`	`+ tma_descriptor_ty,`
	`146`	`+ device_unranked_memref,`
	`147`	`+ list(map(const, self.tma_box_shape)),`
`147`	`148`	`)`
`148`	`149`	`return self.tma_descriptor.result`
`149`	`150`