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‎llvm/test/CodeGen/ARM/load-combine.ll‎

Lines changed: 218 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc < %s -mtriple=arm-unknown | FileCheck %s
3+
; RUN: llc < %s -mtriple=thumbv5-unknown | FileCheck %s --check-prefix=CHECK-THUMBv5
34
; RUN: llc < %s -mtriple=armv6-unknown | FileCheck %s --check-prefix=CHECK-ARMv6
45
; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-THUMBv6
56
; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-THUMBv7
@@ -18,6 +19,20 @@ define i32 @load_i32_by_i8_unaligned(ptr %arg) {
1819
; CHECK-NEXT: orr r0, r1, r0, lsl #24
1920
; CHECK-NEXT: mov pc, lr
2021
;
22+
; CHECK-THUMBv5-LABEL: load_i32_by_i8_unaligned:
23+
; CHECK-THUMBv5: @ %bb.0:
24+
; CHECK-THUMBv5-NEXT: ldrb r1, [r0]
25+
; CHECK-THUMBv5-NEXT: ldrb r2, [r0, #1]
26+
; CHECK-THUMBv5-NEXT: lsls r2, r2, #8
27+
; CHECK-THUMBv5-NEXT: adds r1, r2, r1
28+
; CHECK-THUMBv5-NEXT: ldrb r2, [r0, #2]
29+
; CHECK-THUMBv5-NEXT: lsls r2, r2, #16
30+
; CHECK-THUMBv5-NEXT: adds r1, r1, r2
31+
; CHECK-THUMBv5-NEXT: ldrb r0, [r0, #3]
32+
; CHECK-THUMBv5-NEXT: lsls r0, r0, #24
33+
; CHECK-THUMBv5-NEXT: adds r0, r1, r0
34+
; CHECK-THUMBv5-NEXT: bx lr
35+
;
2136
; CHECK-ARMv6-LABEL: load_i32_by_i8_unaligned:
2237
; CHECK-ARMv6: @ %bb.0:
2338
; CHECK-ARMv6-NEXT: ldrb r2, [r0, #1]
@@ -76,6 +91,11 @@ define i32 @load_i32_by_i8_aligned(ptr %arg) {
7691
; CHECK-NEXT: ldr r0, [r0]
7792
; CHECK-NEXT: mov pc, lr
7893
;
94+
; CHECK-THUMBv5-LABEL: load_i32_by_i8_aligned:
95+
; CHECK-THUMBv5: @ %bb.0:
96+
; CHECK-THUMBv5-NEXT: ldr r0, [r0]
97+
; CHECK-THUMBv5-NEXT: bx lr
98+
;
7999
; CHECK-ARMv6-LABEL: load_i32_by_i8_aligned:
80100
; CHECK-ARMv6: @ %bb.0:
81101
; CHECK-ARMv6-NEXT: ldr r0, [r0]
@@ -123,6 +143,26 @@ define i32 @load_i32_by_i8_bswap(ptr %arg) {
123143
; CHECK-NEXT: eor r0, r1, r0, ror #8
124144
; CHECK-NEXT: mov pc, lr
125145
;
146+
; CHECK-THUMBv5-LABEL: load_i32_by_i8_bswap:
147+
; CHECK-THUMBv5: @ %bb.0:
148+
; CHECK-THUMBv5-NEXT: ldr r0, [r0]
149+
; CHECK-THUMBv5-NEXT: movs r1, #8
150+
; CHECK-THUMBv5-NEXT: movs r2, r0
151+
; CHECK-THUMBv5-NEXT: rors r2, r1
152+
; CHECK-THUMBv5-NEXT: movs r1, #16
153+
; CHECK-THUMBv5-NEXT: movs r3, r0
154+
; CHECK-THUMBv5-NEXT: rors r3, r1
155+
; CHECK-THUMBv5-NEXT: eors r3, r0
156+
; CHECK-THUMBv5-NEXT: ldr r0, .LCPI2_0
157+
; CHECK-THUMBv5-NEXT: ands r0, r3
158+
; CHECK-THUMBv5-NEXT: lsrs r0, r0, #8
159+
; CHECK-THUMBv5-NEXT: eors r0, r2
160+
; CHECK-THUMBv5-NEXT: bx lr
161+
; CHECK-THUMBv5-NEXT: .p2align 2
162+
; CHECK-THUMBv5-NEXT: @ %bb.1:
163+
; CHECK-THUMBv5-NEXT: .LCPI2_0:
164+
; CHECK-THUMBv5-NEXT: .long 4278255360 @ 0xff00ff00
165+
;
126166
; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap:
127167
; CHECK-ARMv6: @ %bb.0:
128168
; CHECK-ARMv6-NEXT: ldr r0, [r0]
@@ -171,6 +211,13 @@ define i64 @load_i64_by_i8(ptr %arg) {
171211
; CHECK-NEXT: mov r0, r2
172212
; CHECK-NEXT: mov pc, lr
173213
;
214+
; CHECK-THUMBv5-LABEL: load_i64_by_i8:
215+
; CHECK-THUMBv5: @ %bb.0:
216+
; CHECK-THUMBv5-NEXT: ldr r2, [r0]
217+
; CHECK-THUMBv5-NEXT: ldr r1, [r0, #4]
218+
; CHECK-THUMBv5-NEXT: movs r0, r2
219+
; CHECK-THUMBv5-NEXT: bx lr
220+
;
174221
; CHECK-ARMv6-LABEL: load_i64_by_i8:
175222
; CHECK-ARMv6: @ %bb.0:
176223
; CHECK-ARMv6-NEXT: ldrd r0, r1, [r0]
@@ -245,6 +292,37 @@ define i64 @load_i64_by_i8_bswap(ptr %arg) {
245292
; CHECK-NEXT: eor r1, r2, r1, ror #8
246293
; CHECK-NEXT: mov pc, lr
247294
;
295+
; CHECK-THUMBv5-LABEL: load_i64_by_i8_bswap:
296+
; CHECK-THUMBv5: @ %bb.0:
297+
; CHECK-THUMBv5-NEXT: push {r4, r5, r7, lr}
298+
; CHECK-THUMBv5-NEXT: ldr r1, [r0, #4]
299+
; CHECK-THUMBv5-NEXT: movs r3, #8
300+
; CHECK-THUMBv5-NEXT: movs r4, r1
301+
; CHECK-THUMBv5-NEXT: rors r4, r3
302+
; CHECK-THUMBv5-NEXT: movs r5, #16
303+
; CHECK-THUMBv5-NEXT: movs r2, r1
304+
; CHECK-THUMBv5-NEXT: rors r2, r5
305+
; CHECK-THUMBv5-NEXT: eors r2, r1
306+
; CHECK-THUMBv5-NEXT: ldr r1, .LCPI4_0
307+
; CHECK-THUMBv5-NEXT: ands r2, r1
308+
; CHECK-THUMBv5-NEXT: lsrs r2, r2, #8
309+
; CHECK-THUMBv5-NEXT: eors r2, r4
310+
; CHECK-THUMBv5-NEXT: ldr r0, [r0]
311+
; CHECK-THUMBv5-NEXT: movs r4, r0
312+
; CHECK-THUMBv5-NEXT: rors r4, r3
313+
; CHECK-THUMBv5-NEXT: movs r3, r0
314+
; CHECK-THUMBv5-NEXT: rors r3, r5
315+
; CHECK-THUMBv5-NEXT: eors r3, r0
316+
; CHECK-THUMBv5-NEXT: ands r3, r1
317+
; CHECK-THUMBv5-NEXT: lsrs r1, r3, #8
318+
; CHECK-THUMBv5-NEXT: eors r1, r4
319+
; CHECK-THUMBv5-NEXT: movs r0, r2
320+
; CHECK-THUMBv5-NEXT: pop {r4, r5, r7, pc}
321+
; CHECK-THUMBv5-NEXT: .p2align 2
322+
; CHECK-THUMBv5-NEXT: @ %bb.1:
323+
; CHECK-THUMBv5-NEXT: .LCPI4_0:
324+
; CHECK-THUMBv5-NEXT: .long 4278255360 @ 0xff00ff00
325+
;
248326
; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap:
249327
; CHECK-ARMv6: @ %bb.0:
250328
; CHECK-ARMv6-NEXT: ldrd r2, r3, [r0]
@@ -315,6 +393,12 @@ define i32 @load_i32_by_i8_nonzero_offset(ptr %arg) {
315393
; CHECK-NEXT: ldr r0, [r0, #1]
316394
; CHECK-NEXT: mov pc, lr
317395
;
396+
; CHECK-THUMBv5-LABEL: load_i32_by_i8_nonzero_offset:
397+
; CHECK-THUMBv5: @ %bb.0:
398+
; CHECK-THUMBv5-NEXT: movs r1, #1
399+
; CHECK-THUMBv5-NEXT: ldr r0, [r0, r1]
400+
; CHECK-THUMBv5-NEXT: bx lr
401+
;
318402
; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset:
319403
; CHECK-ARMv6: @ %bb.0:
320404
; CHECK-ARMv6-NEXT: ldr r0, [r0, #1]
@@ -361,6 +445,12 @@ define i32 @load_i32_by_i8_neg_offset(ptr %arg) {
361445
; CHECK-NEXT: ldr r0, [r0, #-4]
362446
; CHECK-NEXT: mov pc, lr
363447
;
448+
; CHECK-THUMBv5-LABEL: load_i32_by_i8_neg_offset:
449+
; CHECK-THUMBv5: @ %bb.0:
450+
; CHECK-THUMBv5-NEXT: subs r0, r0, #4
451+
; CHECK-THUMBv5-NEXT: ldr r0, [r0]
452+
; CHECK-THUMBv5-NEXT: bx lr
453+
;
364454
; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset:
365455
; CHECK-ARMv6: @ %bb.0:
366456
; CHECK-ARMv6-NEXT: ldr r0, [r0, #-4]
@@ -411,6 +501,26 @@ define i32 @load_i32_by_i8_nonzero_offset_bswap(ptr %arg) {
411501
; CHECK-NEXT: eor r0, r1, r0, ror #8
412502
; CHECK-NEXT: mov pc, lr
413503
;
504+
; CHECK-THUMBv5-LABEL: load_i32_by_i8_nonzero_offset_bswap:
505+
; CHECK-THUMBv5: @ %bb.0:
506+
; CHECK-THUMBv5-NEXT: movs r1, #1
507+
; CHECK-THUMBv5-NEXT: ldr r0, [r0, r1]
508+
; CHECK-THUMBv5-NEXT: movs r1, #16
509+
; CHECK-THUMBv5-NEXT: movs r2, r0
510+
; CHECK-THUMBv5-NEXT: rors r2, r1
511+
; CHECK-THUMBv5-NEXT: eors r2, r0
512+
; CHECK-THUMBv5-NEXT: ldr r1, .LCPI7_0
513+
; CHECK-THUMBv5-NEXT: ands r1, r2
514+
; CHECK-THUMBv5-NEXT: lsrs r1, r1, #8
515+
; CHECK-THUMBv5-NEXT: movs r2, #8
516+
; CHECK-THUMBv5-NEXT: rors r0, r2
517+
; CHECK-THUMBv5-NEXT: eors r0, r1
518+
; CHECK-THUMBv5-NEXT: bx lr
519+
; CHECK-THUMBv5-NEXT: .p2align 2
520+
; CHECK-THUMBv5-NEXT: @ %bb.1:
521+
; CHECK-THUMBv5-NEXT: .LCPI7_0:
522+
; CHECK-THUMBv5-NEXT: .long 4278255360 @ 0xff00ff00
523+
;
414524
; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset_bswap:
415525
; CHECK-ARMv6: @ %bb.0:
416526
; CHECK-ARMv6-NEXT: ldr r0, [r0, #1]
@@ -464,6 +574,27 @@ define i32 @load_i32_by_i8_neg_offset_bswap(ptr %arg) {
464574
; CHECK-NEXT: eor r0, r1, r0, ror #8
465575
; CHECK-NEXT: mov pc, lr
466576
;
577+
; CHECK-THUMBv5-LABEL: load_i32_by_i8_neg_offset_bswap:
578+
; CHECK-THUMBv5: @ %bb.0:
579+
; CHECK-THUMBv5-NEXT: subs r0, r0, #4
580+
; CHECK-THUMBv5-NEXT: ldr r0, [r0]
581+
; CHECK-THUMBv5-NEXT: movs r1, #8
582+
; CHECK-THUMBv5-NEXT: movs r2, r0
583+
; CHECK-THUMBv5-NEXT: rors r2, r1
584+
; CHECK-THUMBv5-NEXT: movs r1, #16
585+
; CHECK-THUMBv5-NEXT: movs r3, r0
586+
; CHECK-THUMBv5-NEXT: rors r3, r1
587+
; CHECK-THUMBv5-NEXT: eors r3, r0
588+
; CHECK-THUMBv5-NEXT: ldr r0, .LCPI8_0
589+
; CHECK-THUMBv5-NEXT: ands r0, r3
590+
; CHECK-THUMBv5-NEXT: lsrs r0, r0, #8
591+
; CHECK-THUMBv5-NEXT: eors r0, r2
592+
; CHECK-THUMBv5-NEXT: bx lr
593+
; CHECK-THUMBv5-NEXT: .p2align 2
594+
; CHECK-THUMBv5-NEXT: @ %bb.1:
595+
; CHECK-THUMBv5-NEXT: .LCPI8_0:
596+
; CHECK-THUMBv5-NEXT: .long 4278255360 @ 0xff00ff00
597+
;
467598
; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset_bswap:
468599
; CHECK-ARMv6: @ %bb.0:
469600
; CHECK-ARMv6-NEXT: ldr r0, [r0, #-4]
@@ -519,6 +650,26 @@ define i32 @load_i32_by_bswap_i16(ptr %arg) {
519650
; CHECK-NEXT: eor r0, r1, r0, ror #8
520651
; CHECK-NEXT: mov pc, lr
521652
;
653+
; CHECK-THUMBv5-LABEL: load_i32_by_bswap_i16:
654+
; CHECK-THUMBv5: @ %bb.0:
655+
; CHECK-THUMBv5-NEXT: ldr r0, [r0]
656+
; CHECK-THUMBv5-NEXT: movs r1, #8
657+
; CHECK-THUMBv5-NEXT: movs r2, r0
658+
; CHECK-THUMBv5-NEXT: rors r2, r1
659+
; CHECK-THUMBv5-NEXT: movs r1, #16
660+
; CHECK-THUMBv5-NEXT: movs r3, r0
661+
; CHECK-THUMBv5-NEXT: rors r3, r1
662+
; CHECK-THUMBv5-NEXT: eors r3, r0
663+
; CHECK-THUMBv5-NEXT: ldr r0, .LCPI9_0
664+
; CHECK-THUMBv5-NEXT: ands r0, r3
665+
; CHECK-THUMBv5-NEXT: lsrs r0, r0, #8
666+
; CHECK-THUMBv5-NEXT: eors r0, r2
667+
; CHECK-THUMBv5-NEXT: bx lr
668+
; CHECK-THUMBv5-NEXT: .p2align 2
669+
; CHECK-THUMBv5-NEXT: @ %bb.1:
670+
; CHECK-THUMBv5-NEXT: .LCPI9_0:
671+
; CHECK-THUMBv5-NEXT: .long 4278255360 @ 0xff00ff00
672+
;
522673
; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:
523674
; CHECK-ARMv6: @ %bb.0:
524675
; CHECK-ARMv6-NEXT: ldr r0, [r0]
@@ -558,6 +709,11 @@ define i32 @load_i32_by_sext_i16(ptr %arg) {
558709
; CHECK-NEXT: ldr r0, [r0]
559710
; CHECK-NEXT: mov pc, lr
560711
;
712+
; CHECK-THUMBv5-LABEL: load_i32_by_sext_i16:
713+
; CHECK-THUMBv5: @ %bb.0:
714+
; CHECK-THUMBv5-NEXT: ldr r0, [r0]
715+
; CHECK-THUMBv5-NEXT: bx lr
716+
;
561717
; CHECK-ARMv6-LABEL: load_i32_by_sext_i16:
562718
; CHECK-ARMv6: @ %bb.0:
563719
; CHECK-ARMv6-NEXT: ldr r0, [r0]
@@ -592,6 +748,12 @@ define i32 @load_i32_by_i8_base_offset_index(ptr %arg, i32 %i) {
592748
; CHECK-NEXT: ldr r0, [r0, #12]
593749
; CHECK-NEXT: mov pc, lr
594750
;
751+
; CHECK-THUMBv5-LABEL: load_i32_by_i8_base_offset_index:
752+
; CHECK-THUMBv5: @ %bb.0:
753+
; CHECK-THUMBv5-NEXT: adds r0, r0, r1
754+
; CHECK-THUMBv5-NEXT: ldr r0, [r0, #12]
755+
; CHECK-THUMBv5-NEXT: bx lr
756+
;
595757
; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index:
596758
; CHECK-ARMv6: @ %bb.0:
597759
; CHECK-ARMv6-NEXT: add r0, r0, r1
@@ -649,6 +811,13 @@ define i32 @load_i32_by_i8_base_offset_index_2(ptr %arg, i32 %i) {
649811
; CHECK-NEXT: ldr r0, [r0, #13]
650812
; CHECK-NEXT: mov pc, lr
651813
;
814+
; CHECK-THUMBv5-LABEL: load_i32_by_i8_base_offset_index_2:
815+
; CHECK-THUMBv5: @ %bb.0:
816+
; CHECK-THUMBv5-NEXT: adds r0, r1, r0
817+
; CHECK-THUMBv5-NEXT: movs r1, #13
818+
; CHECK-THUMBv5-NEXT: ldr r0, [r0, r1]
819+
; CHECK-THUMBv5-NEXT: bx lr
820+
;
652821
; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index_2:
653822
; CHECK-ARMv6: @ %bb.0:
654823
; CHECK-ARMv6-NEXT: add r0, r1, r0
@@ -705,6 +874,11 @@ define i32 @zext_load_i32_by_i8(ptr %arg) {
705874
; CHECK-NEXT: ldrh r0, [r0]
706875
; CHECK-NEXT: mov pc, lr
707876
;
877+
; CHECK-THUMBv5-LABEL: zext_load_i32_by_i8:
878+
; CHECK-THUMBv5: @ %bb.0:
879+
; CHECK-THUMBv5-NEXT: ldrh r0, [r0]
880+
; CHECK-THUMBv5-NEXT: bx lr
881+
;
708882
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8:
709883
; CHECK-ARMv6: @ %bb.0:
710884
; CHECK-ARMv6-NEXT: ldrh r0, [r0]
@@ -741,6 +915,15 @@ define i32 @zext_load_i32_by_i8_shl_8(ptr %arg) {
741915
; CHECK-NEXT: orr r0, r0, r1, lsl #8
742916
; CHECK-NEXT: mov pc, lr
743917
;
918+
; CHECK-THUMBv5-LABEL: zext_load_i32_by_i8_shl_8:
919+
; CHECK-THUMBv5: @ %bb.0:
920+
; CHECK-THUMBv5-NEXT: ldrb r1, [r0]
921+
; CHECK-THUMBv5-NEXT: lsls r1, r1, #8
922+
; CHECK-THUMBv5-NEXT: ldrb r0, [r0, #1]
923+
; CHECK-THUMBv5-NEXT: lsls r0, r0, #16
924+
; CHECK-THUMBv5-NEXT: adds r0, r0, r1
925+
; CHECK-THUMBv5-NEXT: bx lr
926+
;
744927
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_shl_8:
745928
; CHECK-ARMv6: @ %bb.0:
746929
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
@@ -788,6 +971,15 @@ define i32 @zext_load_i32_by_i8_shl_16(ptr %arg) {
788971
; CHECK-NEXT: orr r0, r0, r1, lsl #16
789972
; CHECK-NEXT: mov pc, lr
790973
;
974+
; CHECK-THUMBv5-LABEL: zext_load_i32_by_i8_shl_16:
975+
; CHECK-THUMBv5: @ %bb.0:
976+
; CHECK-THUMBv5-NEXT: ldrb r1, [r0]
977+
; CHECK-THUMBv5-NEXT: lsls r1, r1, #16
978+
; CHECK-THUMBv5-NEXT: ldrb r0, [r0, #1]
979+
; CHECK-THUMBv5-NEXT: lsls r0, r0, #24
980+
; CHECK-THUMBv5-NEXT: adds r0, r0, r1
981+
; CHECK-THUMBv5-NEXT: bx lr
982+
;
791983
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_shl_16:
792984
; CHECK-ARMv6: @ %bb.0:
793985
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
@@ -834,6 +1026,14 @@ define i32 @zext_load_i32_by_i8_bswap(ptr %arg) {
8341026
; CHECK-NEXT: orr r0, r0, r1, lsl #8
8351027
; CHECK-NEXT: mov pc, lr
8361028
;
1029+
; CHECK-THUMBv5-LABEL: zext_load_i32_by_i8_bswap:
1030+
; CHECK-THUMBv5: @ %bb.0:
1031+
; CHECK-THUMBv5-NEXT: ldrb r1, [r0, #1]
1032+
; CHECK-THUMBv5-NEXT: ldrb r0, [r0]
1033+
; CHECK-THUMBv5-NEXT: lsls r0, r0, #8
1034+
; CHECK-THUMBv5-NEXT: adds r0, r0, r1
1035+
; CHECK-THUMBv5-NEXT: bx lr
1036+
;
8371037
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap:
8381038
; CHECK-ARMv6: @ %bb.0:
8391039
; CHECK-ARMv6-NEXT: ldrh r0, [r0]
@@ -873,6 +1073,15 @@ define i32 @zext_load_i32_by_i8_bswap_shl_8(ptr %arg) {
8731073
; CHECK-NEXT: orr r0, r1, r0, lsl #8
8741074
; CHECK-NEXT: mov pc, lr
8751075
;
1076+
; CHECK-THUMBv5-LABEL: zext_load_i32_by_i8_bswap_shl_8:
1077+
; CHECK-THUMBv5: @ %bb.0:
1078+
; CHECK-THUMBv5-NEXT: ldrb r1, [r0, #1]
1079+
; CHECK-THUMBv5-NEXT: lsls r1, r1, #8
1080+
; CHECK-THUMBv5-NEXT: ldrb r0, [r0]
1081+
; CHECK-THUMBv5-NEXT: lsls r0, r0, #16
1082+
; CHECK-THUMBv5-NEXT: adds r0, r0, r1
1083+
; CHECK-THUMBv5-NEXT: bx lr
1084+
;
8761085
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap_shl_8:
8771086
; CHECK-ARMv6: @ %bb.0:
8781087
; CHECK-ARMv6-NEXT: ldrb r1, [r0]
@@ -920,6 +1129,15 @@ define i32 @zext_load_i32_by_i8_bswap_shl_16(ptr %arg) {
9201129
; CHECK-NEXT: orr r0, r1, r0, lsl #16
9211130
; CHECK-NEXT: mov pc, lr
9221131
;
1132+
; CHECK-THUMBv5-LABEL: zext_load_i32_by_i8_bswap_shl_16:
1133+
; CHECK-THUMBv5: @ %bb.0:
1134+
; CHECK-THUMBv5-NEXT: ldrb r1, [r0, #1]
1135+
; CHECK-THUMBv5-NEXT: lsls r1, r1, #16
1136+
; CHECK-THUMBv5-NEXT: ldrb r0, [r0]
1137+
; CHECK-THUMBv5-NEXT: lsls r0, r0, #24
1138+
; CHECK-THUMBv5-NEXT: adds r0, r0, r1
1139+
; CHECK-THUMBv5-NEXT: bx lr
1140+
;
9231141
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap_shl_16:
9241142
; CHECK-ARMv6: @ %bb.0:
9251143
; CHECK-ARMv6-NEXT: ldrb r1, [r0]

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