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| 1 | +//===- GPUToAMDGPU.cpp - GPU to AMDGPU dialect conversion -------===// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +//===----------------------------------------------------------------------===// |
| 8 | + |
| 9 | +#include "mlir/Conversion/GPUToAMDGPU/GPUToAMDGPU.h" |
| 10 | + |
| 11 | +#include "mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h" |
| 12 | +#include "mlir/Dialect/LLVMIR/LLVMDialect.h" |
| 13 | +#include "mlir/Dialect/LLVMIR/ROCDLDialect.h" |
| 14 | +#include "mlir/IR/BuiltinTypes.h" |
| 15 | +#include "mlir/IR/TypeUtilities.h" |
| 16 | +#include "mlir/Pass/Pass.h" |
| 17 | + |
| 18 | +#include "mlir/Conversion/GPUCommon/GPUCommonPass.h" |
| 19 | +#include "mlir/Dialect/GPU/IR/GPUDialect.h" |
| 20 | +#include "mlir/Dialect/Vector/IR/VectorOps.h" |
| 21 | + |
| 22 | +#include "mlir/Transforms/WalkPatternRewriteDriver.h" |
| 23 | +#include "llvm/Support/FormatVariadic.h" |
| 24 | + |
| 25 | +namespace mlir { |
| 26 | +#define GEN_PASS_DEF_CONVERTGPUTOAMDGPUPASS |
| 27 | +#include "mlir/Conversion/Passes.h.inc" |
| 28 | +} // namespace mlir |
| 29 | + |
| 30 | +using namespace mlir; |
| 31 | + |
| 32 | +namespace { |
| 33 | +struct ClusterInfo { |
| 34 | + unsigned clusterStride; |
| 35 | + unsigned clusterSize; |
| 36 | + unsigned subgroupSize; |
| 37 | +}; |
| 38 | + |
| 39 | +static FailureOr<ClusterInfo> |
| 40 | +getAndValidateClusterInfo(gpu::SubgroupReduceOp op, unsigned subgroupSize) { |
| 41 | + assert(llvm::isPowerOf2_32(subgroupSize)); |
| 42 | + |
| 43 | + std::optional<uint32_t> clusterSize = op.getClusterSize(); |
| 44 | + assert(!clusterSize || |
| 45 | + llvm::isPowerOf2_32(*clusterSize)); // Verifier should've caught this. |
| 46 | + if (clusterSize && *clusterSize > subgroupSize) |
| 47 | + return op.emitOpError() |
| 48 | + << "cluster size " << *clusterSize |
| 49 | + << " is greater than subgroup size " << subgroupSize; |
| 50 | + unsigned effectiveClusterSize = clusterSize.value_or(subgroupSize); |
| 51 | + |
| 52 | + auto clusterStride = op.getClusterStride(); |
| 53 | + assert(llvm::isPowerOf2_32(clusterStride)); // Verifier should've caught this. |
| 54 | + if (clusterStride >= subgroupSize) |
| 55 | + return op.emitOpError() |
| 56 | + << "cluster stride " << clusterStride |
| 57 | + << " is not less than subgroup size " << subgroupSize; |
| 58 | + |
| 59 | + return ClusterInfo{clusterStride, effectiveClusterSize, subgroupSize}; |
| 60 | +} |
| 61 | + |
| 62 | +Value createSubgroupDPPReduction(OpBuilder &b, Location loc, Value input, |
| 63 | + gpu::AllReduceOperation mode, |
| 64 | + const ClusterInfo &ci) { |
| 65 | + Value result = input; |
| 66 | + if (ci.clusterSize >= 2) { |
| 67 | + auto permArg = b.getIntegerAttr(b.getIntegerType(32), 1); |
| 68 | + Value dppResult = |
| 69 | + b. create<amdgpu::DPPOp>(loc, result. getType(), result, result, |
| 70 | + amdgpu::DPPPerm::row_shr, permArg); |
| 71 | + result = vector::makeArithReduction(b, loc, gpu::convertReductionKind(mode), |
| 72 | + result, dppResult); |
| 73 | + } |
| 74 | + |
| 75 | + if (ci.clusterSize >= 4) { |
| 76 | + auto permArg = b.getIntegerAttr(b.getIntegerType(32), 2); |
| 77 | + Value dppResult = |
| 78 | + b. create<amdgpu::DPPOp>(loc, result. getType(), result, result, |
| 79 | + amdgpu::DPPPerm::row_shr, permArg); |
| 80 | + result = vector::makeArithReduction(b, loc, gpu::convertReductionKind(mode), |
| 81 | + result, dppResult); |
| 82 | + } |
| 83 | + |
| 84 | + if (ci.clusterSize >= 8) { |
| 85 | + Value dppResult = b. create<amdgpu::DPPOp>( |
| 86 | + loc, result.getType(), result, result, amdgpu::DPPPerm::row_half_mirror, |
| 87 | + b.getUnitAttr()); |
| 88 | + result = vector::makeArithReduction(b, loc, gpu::convertReductionKind(mode), |
| 89 | + result, dppResult); |
| 90 | + } |
| 91 | + |
| 92 | + if (ci.clusterSize >= 16) { |
| 93 | + Value dppResult = |
| 94 | + b. create<amdgpu::DPPOp>(loc, result. getType(), result, result, |
| 95 | + amdgpu::DPPPerm::row_mirror, b.getUnitAttr()); |
| 96 | + result = vector::makeArithReduction(b, loc, gpu::convertReductionKind(mode), |
| 97 | + result, dppResult); |
| 98 | + } |
| 99 | + |
| 100 | + if (ci.clusterSize >= 32) { |
| 101 | + auto permArg = b.getIntegerAttr(b.getIntegerType(32), 15); |
| 102 | + Value dppResult = b. create<amdgpu::DPPOp>( |
| 103 | + loc, result.getType(), result, result, amdgpu::DPPPerm::row_bcast_15, |
| 104 | + b.getUnitAttr(), 10, 15, false); |
| 105 | + result = vector::makeArithReduction(b, loc, gpu::convertReductionKind(mode), |
| 106 | + result, dppResult); |
| 107 | + } |
| 108 | + |
| 109 | + if (ci.clusterSize == 64) { |
| 110 | + auto permArg = b.getIntegerAttr(b.getIntegerType(32), 31); |
| 111 | + Value dppResult = b. create<amdgpu::DPPOp>( |
| 112 | + loc, result.getType(), result, result, amdgpu::DPPPerm::row_bcast_31, |
| 113 | + b.getUnitAttr(), 12, 15, false); |
| 114 | + result = vector::makeArithReduction(b, loc, gpu::convertReductionKind(mode), |
| 115 | + result, dppResult); |
| 116 | + } |
| 117 | + |
| 118 | + auto int32Type = IntegerType::get(b.getContext(), 32); |
| 119 | + Value lane63 = b.create<LLVM::ConstantOp>(loc, int32Type, 63); |
| 120 | + result = b.create<ROCDL::ReadlaneOp>(loc, input.getType(), result, lane63); |
| 121 | + assert(result.getType() == input.getType()); |
| 122 | + return result; |
| 123 | +} |
| 124 | + |
| 125 | +struct ScalarSubgroupReduceToShuffles final |
| 126 | + : OpRewritePattern<gpu::SubgroupReduceOp> { |
| 127 | + ScalarSubgroupReduceToShuffles(MLIRContext *ctx, unsigned subgroupSize, |
| 128 | + bool matchClustered, PatternBenefit benefit) |
| 129 | + : OpRewritePattern(ctx, benefit), subgroupSize(subgroupSize), |
| 130 | + matchClustered(matchClustered) {} |
| 131 | + |
| 132 | + LogicalResult matchAndRewrite(gpu::SubgroupReduceOp op, |
| 133 | + PatternRewriter &rewriter) const override { |
| 134 | + if (op.getClusterSize().has_value() != matchClustered) { |
| 135 | + return rewriter.notifyMatchFailure( |
| 136 | + op, llvm::formatv("op is {0}clustered but pattern is configured to " |
| 137 | + "only match {1}clustered ops", |
| 138 | + matchClustered ? "non-" : "", |
| 139 | + matchClustered ? "" : "non-")); |
| 140 | + } |
| 141 | + |
| 142 | + auto ci = getAndValidateClusterInfo(op, subgroupSize); |
| 143 | + if (failed(ci)) |
| 144 | + return failure(); |
| 145 | + |
| 146 | + Location loc = op.getLoc(); |
| 147 | + rewriter.replaceOp(op, createSubgroupDPPReduction( |
| 148 | + rewriter, loc, op.getValue(), op.getOp(), *ci)); |
| 149 | + return success(); |
| 150 | + } |
| 151 | + |
| 152 | +private: |
| 153 | + unsigned subgroupSize = 0; |
| 154 | + bool matchClustered = false; |
| 155 | +}; |
| 156 | + |
| 157 | +struct ConvertGPUToAMDGPUPass |
| 158 | + : public impl::ConvertGPUToAMDGPUPassBase<ConvertGPUToAMDGPUPass> { |
| 159 | + using Base::Base; |
| 160 | + |
| 161 | + void runOnOperation() override { |
| 162 | + RewritePatternSet patterns(&getContext()); |
| 163 | + int subgroupSizeInt = static_cast<int>(subgroupSize); |
| 164 | + populateAMDGPUOptimizedSubgroupReducePatterns(patterns, subgroupSizeInt, |
| 165 | + PatternBenefit(1)); |
| 166 | + walkAndApplyPatterns(getOperation(), std::move(patterns)); |
| 167 | + } |
| 168 | +}; |
| 169 | +} // namespace |
| 170 | + |
| 171 | +void mlir::populateAMDGPUOptimizedSubgroupReducePatterns(RewritePatternSet &patterns, |
| 172 | + unsigned subgroupSize, |
| 173 | + PatternBenefit benefit) { |
| 174 | + patterns.add<ScalarSubgroupReduceToShuffles>( |
| 175 | + patterns.getContext(), subgroupSize, /*matchClustered=*/true, benefit); |
| 176 | +} |
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