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[LoongArch][NFC] Add tests for 256-bit broadcast with undef high part
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llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvrepl128vei.ll

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@@ -12,6 +12,18 @@ define <32 x i8> @shufflevector_v32i8(<32 x i8> %a, <32 x i8> %b) {
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ret <32 x i8> %c
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}
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;; xvrepl128vei.b
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define <32 x i8> @shufflevector_v32i8_undef(<32 x i8> %a) {
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; CHECK-LABEL: shufflevector_v32i8_undef:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvpermi.d $xr0, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.b $xr0, $xr0, 1
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; CHECK-NEXT: ret
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%c = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1,
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i32 33, i32 33, i32 33, i32 33, i32 33, i32 33, i32 33, i32 33, i32 33, i32 33, i32 33, i32 33, i32 33, i32 33, i32 33, i32 33>
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ret <32 x i8> %c
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}
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;; xvrepl128vei.h
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define <16 x i16> @shufflevector_v16i16(<16 x i16> %a, <16 x i16> %b) {
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; CHECK-LABEL: shufflevector_v16i16:
@@ -23,6 +35,18 @@ define <16 x i16> @shufflevector_v16i16(<16 x i16> %a, <16 x i16> %b) {
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ret <16 x i16> %c
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}
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;; xvrepl128vei.h
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define <16 x i16> @shufflevector_v16i16_undef(<16 x i16> %a) {
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; CHECK-LABEL: shufflevector_v16i16_undef:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvpermi.d $xr0, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.h $xr0, $xr0, 3
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; CHECK-NEXT: ret
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%c = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3,
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i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
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ret <16 x i16> %c
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}
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;; xvrepl128vei.w
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define <8 x i32> @shufflevector_v8i32(<8 x i32> %a, <8 x i32> %b) {
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; CHECK-LABEL: shufflevector_v8i32:
@@ -34,6 +58,17 @@ define <8 x i32> @shufflevector_v8i32(<8 x i32> %a, <8 x i32> %b) {
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ret <8 x i32> %c
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}
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;; xvrepl128vei.w
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define <8 x i32> @shufflevector_v8i32_undef(<8 x i32> %a) {
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; CHECK-LABEL: shufflevector_v8i32_undef:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvpermi.d $xr0, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.w $xr0, $xr0, 2
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; CHECK-NEXT: ret
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%c = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 8, i32 8, i32 8, i32 8>
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ret <8 x i32> %c
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}
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;; xvrepl128vei.d
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define <4 x i64> @shufflevector_v4i64(<4 x i64> %a, <4 x i64> %b) {
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; CHECK-LABEL: shufflevector_v4i64:
@@ -44,6 +79,17 @@ define <4 x i64> @shufflevector_v4i64(<4 x i64> %a, <4 x i64> %b) {
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ret <4 x i64> %c
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}
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;; xvrepl128vei.d
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define <4 x i64> @shufflevector_v4i64_undef(<4 x i64> %a) {
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; CHECK-LABEL: shufflevector_v4i64_undef:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvpermi.d $xr0, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.d $xr0, $xr0, 1
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; CHECK-NEXT: ret
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%c = shufflevector <4 x i64> %a, <4 x i64> poison, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
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ret <4 x i64> %c
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}
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;; xvrepl128vei.w
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define <8 x float> @shufflevector_v8f32(<8 x float> %a, <8 x float> %b) {
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; CHECK-LABEL: shufflevector_v8f32:
@@ -54,6 +100,17 @@ define <8 x float> @shufflevector_v8f32(<8 x float> %a, <8 x float> %b) {
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ret <8 x float> %c
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}
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;; xvrepl128vei.w
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define <8 x float> @shufflevector_v8f32_undef(<8 x float> %a) {
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; CHECK-LABEL: shufflevector_v8f32_undef:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvpermi.d $xr0, $xr0, 78
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; CHECK-NEXT: xvrepl128vei.w $xr0, $xr0, 1
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; CHECK-NEXT: ret
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%c = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 9, i32 9, i32 9, i32 9>
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ret <8 x float> %c
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}
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;; xvrepl128vei.d
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define <4 x double> @shufflevector_v4f64(<4 x double> %a, <4 x double> %b) {
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; CHECK-LABEL: shufflevector_v4f64:
@@ -63,3 +120,14 @@ define <4 x double> @shufflevector_v4f64(<4 x double> %a, <4 x double> %b) {
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%c = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 5, i32 5, i32 7, i32 7>
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ret <4 x double> %c
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}
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;; xvrepl128vei.d
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define <4 x double> @shufflevector_v4f64_undef(<4 x double> %a) {
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; CHECK-LABEL: shufflevector_v4f64_undef:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvpermi.d $xr0, $xr0, 68
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; CHECK-NEXT: xvrepl128vei.d $xr0, $xr0, 0
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; CHECK-NEXT: ret
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%c = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> <i32 0, i32 0, i32 7, i32 7>
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ret <4 x double> %c
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}

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