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topperctopperc
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fixup! Add PseudoMV. Add load/store to more places.
1 parent e705573 commit 4aab31b

21 files changed

+286
-190
lines changed

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,8 @@ class RISCVExpandPseudo : public MachineFunctionPass {
5050
MachineBasicBlock::iterator MBBI, unsigned Opcode);
5151
bool expandMV_FPR16INX(MachineBasicBlock &MBB,
5252
MachineBasicBlock::iterator MBBI);
53+
bool expandMV_FPR32INX(MachineBasicBlock &MBB,
54+
MachineBasicBlock::iterator MBBI);
5355
bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
5456
MachineBasicBlock::iterator MBBI);
5557
bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
@@ -108,6 +110,8 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
108110
switch (MBBI->getOpcode()) {
109111
case RISCV::PseudoMV_FPR16INX:
110112
return expandMV_FPR16INX(MBB, MBBI);
113+
case RISCV::PseudoMV_FPR32INX:
114+
return expandMV_FPR32INX(MBB, MBBI);
111115
case RISCV::PseudoRV32ZdinxSD:
112116
return expandRV32ZdinxStore(MBB, MBBI);
113117
case RISCV::PseudoRV32ZdinxLD:
@@ -287,6 +291,23 @@ bool RISCVExpandPseudo::expandMV_FPR16INX(MachineBasicBlock &MBB,
287291
return true;
288292
}
289293

294+
bool RISCVExpandPseudo::expandMV_FPR32INX(MachineBasicBlock &MBB,
295+
MachineBasicBlock::iterator MBBI) {
296+
DebugLoc DL = MBBI->getDebugLoc();
297+
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
298+
Register DstReg = TRI->getMatchingSuperReg(
299+
MBBI->getOperand(0).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
300+
Register SrcReg = TRI->getMatchingSuperReg(
301+
MBBI->getOperand(1).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
302+
303+
BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
304+
.addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
305+
.addImm(0);
306+
307+
MBBI->eraseFromParent(); // The pseudo instruction is gone now.
308+
return true;
309+
}
310+
290311
// This function expands the PseudoRV32ZdinxSD for storing a double-precision
291312
// floating-point value into memory by generating an equivalent instruction
292313
// sequence for RV32.

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,7 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
110110
MemBytes = 2;
111111
break;
112112
case RISCV::LW:
113+
case RISCV::LW_INX:
113114
case RISCV::FLW:
114115
case RISCV::LWU:
115116
MemBytes = 4;
@@ -150,6 +151,7 @@ Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
150151
MemBytes = 2;
151152
break;
152153
case RISCV::SW:
154+
case RISCV::SW_INX:
153155
case RISCV::FSW:
154156
MemBytes = 4;
155157
break;
@@ -472,10 +474,9 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
472474
}
473475

474476
if (RISCV::GPRF32RegClass.contains(DstReg, SrcReg)) {
475-
assert(STI.hasStdExtZfinx());
476-
BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_S_INX), DstReg)
477-
.addReg(SrcReg, getKillRegState(KillSrc))
478-
.addReg(SrcReg, getKillRegState(KillSrc));
477+
BuildMI(MBB, MBBI, DL, get(RISCV::PseudoMV_FPR32INX), DstReg)
478+
.addReg(SrcReg,
479+
getKillRegState(KillSrc) | getRenamableRegState(RenamableSrc));
479480
return;
480481
}
481482

@@ -1535,6 +1536,7 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
15351536

15361537
switch (Opcode) {
15371538
case RISCV::PseudoMV_FPR16INX:
1539+
case RISCV::PseudoMV_FPR32INX:
15381540
// MV is always compressible.
15391541
return STI.hasStdExtCOrZca() ? 2 : 4;
15401542
case TargetOpcode::STACKMAP:
@@ -2595,6 +2597,7 @@ bool RISCVInstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
25952597
case RISCV::LH_INX:
25962598
case RISCV::LHU:
25972599
case RISCV::LW:
2600+
case RISCV::LW_INX:
25982601
case RISCV::LWU:
25992602
case RISCV::LD:
26002603
case RISCV::FLH:
@@ -2604,6 +2607,7 @@ bool RISCVInstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
26042607
case RISCV::SH:
26052608
case RISCV::SH_INX:
26062609
case RISCV::SW:
2610+
case RISCV::SW_INX:
26072611
case RISCV::SD:
26082612
case RISCV::FSH:
26092613
case RISCV::FSW:
@@ -2673,9 +2677,11 @@ bool RISCVInstrInfo::getMemOperandsWithOffsetWidth(
26732677
case RISCV::SH_INX:
26742678
case RISCV::FSH:
26752679
case RISCV::LW:
2680+
case RISCV::LW_INX:
26762681
case RISCV::LWU:
26772682
case RISCV::FLW:
26782683
case RISCV::SW:
2684+
case RISCV::SW_INX:
26792685
case RISCV::FSW:
26802686
case RISCV::LD:
26812687
case RISCV::FLD:

‎llvm/lib/Target/RISCV/RISCVInstrInfoC.td‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -331,6 +331,15 @@ def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00>,
331331
let Inst{5} = imm{6};
332332
}
333333

334+
let isCodeGenOnly = 1 in
335+
def C_LW_INX : CLoad_ri<0b010, "c.lw", GPRF32C, uimm7_lsb00>,
336+
Sched<[WriteLDW, ReadMemBase]> {
337+
bits<7> imm;
338+
let Inst{12-10} = imm{5-3};
339+
let Inst{6} = imm{2};
340+
let Inst{5} = imm{6};
341+
}
342+
334343
let DecoderNamespace = "RISCV32Only_",
335344
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
336345
def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
@@ -365,6 +374,15 @@ def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00>,
365374
let Inst{5} = imm{6};
366375
}
367376

377+
let isCodeGenOnly = 1 in
378+
def C_SW_INX : CStore_rri<0b110, "c.sw", GPRF32C, uimm7_lsb00>,
379+
Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
380+
bits<7> imm;
381+
let Inst{12-10} = imm{5-3};
382+
let Inst{6} = imm{2};
383+
let Inst{5} = imm{6};
384+
}
385+
368386
let DecoderNamespace = "RISCV32Only_",
369387
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
370388
def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
@@ -517,6 +535,13 @@ def C_LWSP : CStackLoad<0b010, "c.lwsp", GPRNoX0, uimm8_lsb00>,
517535
let Inst{3-2} = imm{7-6};
518536
}
519537

538+
let isCodeGenOnly = 1 in
539+
def C_LWSP_INX : CStackLoad<0b010, "c.lwsp", GPRF32NoX0, uimm8_lsb00>,
540+
Sched<[WriteLDW, ReadMemBase]> {
541+
let Inst{6-4} = imm{4-2};
542+
let Inst{3-2} = imm{7-6};
543+
}
544+
520545
let DecoderNamespace = "RISCV32Only_",
521546
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
522547
def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
@@ -575,6 +600,13 @@ def C_SWSP : CStackStore<0b110, "c.swsp", GPR, uimm8_lsb00>,
575600
let Inst{8-7} = imm{7-6};
576601
}
577602

603+
let isCodeGenOnly = 1 in
604+
def C_SWSP_INX : CStackStore<0b110, "c.swsp", GPRF32, uimm8_lsb00>,
605+
Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
606+
let Inst{12-9} = imm{5-2};
607+
let Inst{8-7} = imm{7-6};
608+
}
609+
578610
let DecoderNamespace = "RISCV32Only_",
579611
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
580612
def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
@@ -869,6 +901,10 @@ def : CompressPat<(FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm),
869901
let Predicates = [HasStdExtCOrZca] in {
870902
def : CompressPat<(LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
871903
(C_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
904+
905+
let isCompressOnly = true in
906+
def : CompressPat<(LW_INX GPRF32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
907+
(C_LW_INX GPRF32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
872908
} // Predicates = [HasStdExtCOrZca]
873909

874910
let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
@@ -889,6 +925,10 @@ def : CompressPat<(FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm),
889925
let Predicates = [HasStdExtCOrZca] in {
890926
def : CompressPat<(SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
891927
(C_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
928+
929+
let isCompressOnly = true in
930+
def : CompressPat<(SW_INX GPRF32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
931+
(C_SW_INX GPRF32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
892932
} // Predicates = [HasStdExtCOrZca]
893933

894934
let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
@@ -992,6 +1032,10 @@ def : CompressPat<(FLD FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
9921032
let Predicates = [HasStdExtCOrZca] in {
9931033
def : CompressPat<(LW GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
9941034
(C_LWSP GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
1035+
1036+
let isCompressOnly = true in
1037+
def : CompressPat<(LW_INX GPRF32NoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
1038+
(C_LWSP_INX GPRF32NoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
9951039
} // Predicates = [HasStdExtCOrZca]
9961040

9971041
let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
@@ -1034,6 +1078,10 @@ def : CompressPat<(FSD FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
10341078
let Predicates = [HasStdExtCOrZca] in {
10351079
def : CompressPat<(SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
10361080
(C_SWSP GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
1081+
1082+
let isCompressOnly = true in
1083+
def : CompressPat<(SW_INX GPRF32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
1084+
(C_SWSP_INX GPRF32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
10371085
} // Predicates = [HasStdExtCOrZca]
10381086

10391087
let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {

‎llvm/lib/Target/RISCV/RISCVInstrInfoF.td‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -309,6 +309,13 @@ let Predicates = [HasStdExtZfinx], isCodeGenOnly = 1 in {
309309
def LW_INX : Load_ri<0b010, "lw", GPRF32>, Sched<[WriteLDW, ReadMemBase]>;
310310
def SW_INX : Store_rri<0b010, "sw", GPRF32>,
311311
Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
312+
313+
// ADDI with GPRF16 register class to use for copy. This should not be used as
314+
// general ADDI, so the immediate should always be zero.
315+
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveReg = 1,
316+
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
317+
def PseudoMV_FPR32INX : Pseudo<(outs GPRF32:$rd), (ins GPRF32:$rs), []>,
318+
Sched<[WriteIALU, ReadIALU]>;
312319
}
313320

314321
foreach Ext = FExts in {

‎llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,9 @@ static unsigned log2LdstWidth(unsigned Opcode) {
109109
case RISCV::SH_INX:
110110
return 1;
111111
case RISCV::LW:
112+
case RISCV::LW_INX:
112113
case RISCV::SW:
114+
case RISCV::SW_INX:
113115
case RISCV::FLW:
114116
case RISCV::FSW:
115117
return 2;
@@ -136,7 +138,9 @@ static unsigned offsetMask(unsigned Opcode) {
136138
case RISCV::SH_INX:
137139
return maskTrailingOnes<unsigned>(1U);
138140
case RISCV::LW:
141+
case RISCV::LW_INX:
139142
case RISCV::SW:
143+
case RISCV::SW_INX:
140144
case RISCV::FLW:
141145
case RISCV::FSW:
142146
case RISCV::LD:
@@ -178,6 +182,7 @@ static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode) {
178182
static bool isCompressedReg(Register Reg) {
179183
return RISCV::GPRCRegClass.contains(Reg) ||
180184
RISCV::GPRF16CRegClass.contains(Reg) ||
185+
RISCV::GPRF32CRegClass.contains(Reg) ||
181186
RISCV::FPR32CRegClass.contains(Reg) ||
182187
RISCV::FPR64CRegClass.contains(Reg);
183188
}
@@ -195,6 +200,7 @@ static bool isCompressibleLoad(const MachineInstr &MI) {
195200
case RISCV::LHU:
196201
return STI.hasStdExtZcb();
197202
case RISCV::LW:
203+
case RISCV::LW_INX:
198204
case RISCV::LD:
199205
return STI.hasStdExtCOrZca();
200206
case RISCV::FLW:
@@ -216,6 +222,7 @@ static bool isCompressibleStore(const MachineInstr &MI) {
216222
case RISCV::SH_INX:
217223
return STI.hasStdExtZcb();
218224
case RISCV::SW:
225+
case RISCV::SW_INX:
219226
case RISCV::SD:
220227
return STI.hasStdExtCOrZca();
221228
case RISCV::FSW:
@@ -329,6 +336,8 @@ static Register analyzeCompressibleUses(MachineInstr &FirstMI,
329336
RCToScavenge = &RISCV::GPRCRegClass;
330337
else if (RISCV::GPRF16RegClass.contains(RegImm.Reg))
331338
RCToScavenge = &RISCV::GPRF16CRegClass;
339+
else if (RISCV::GPRF32RegClass.contains(RegImm.Reg))
340+
RCToScavenge = &RISCV::GPRF32CRegClass;
332341
else if (RISCV::FPR32RegClass.contains(RegImm.Reg))
333342
RCToScavenge = &RISCV::FPR32CRegClass;
334343
else if (RISCV::FPR64RegClass.contains(RegImm.Reg))

‎llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -387,6 +387,7 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi,
387387
case RISCV::LH:
388388
case RISCV::LH_INX:
389389
case RISCV::LW:
390+
case RISCV::LW_INX:
390391
case RISCV::LBU:
391392
case RISCV::LHU:
392393
case RISCV::LWU:
@@ -398,6 +399,7 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi,
398399
case RISCV::SH:
399400
case RISCV::SH_INX:
400401
case RISCV::SW:
402+
case RISCV::SW_INX:
401403
case RISCV::SD:
402404
case RISCV::FSH:
403405
case RISCV::FSW:

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -663,6 +663,9 @@ def GPRF32 : RISCVRegisterClass<[f32], 32, (add (sequence "X%u_W", 10, 17),
663663
(sequence "X%u_W", 8, 9),
664664
(sequence "X%u_W", 18, 27),
665665
(sequence "X%u_W", 0, 4))>;
666+
def GPRF32C : RISCVRegisterClass<[f32], 32, (add (sequence "X%u_W", 10, 15),
667+
(sequence "X%u_W", 8, 9))>;
668+
def GPRF32NoX0 : RISCVRegisterClass<[f32], 32, (sub GPRF32, X0_W)>;
666669

667670
// Dummy zero register for use in the register pair containing X0 (as X1 is
668671
// not read to or written when the X0 register pair is used).

‎llvm/test/CodeGen/RISCV/float-br-fcmp.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1003,12 +1003,12 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
10031003
; RV32IZFINX: # %bb.0: # %entry
10041004
; RV32IZFINX-NEXT: addi sp, sp, -16
10051005
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1006-
; RV32IZFINX-NEXT: fmv.s a0, zero
1006+
; RV32IZFINX-NEXT: li a0, 0
10071007
; RV32IZFINX-NEXT: call dummy
10081008
; RV32IZFINX-NEXT: feq.s a0, a0, zero
10091009
; RV32IZFINX-NEXT: beqz a0, .LBB17_3
10101010
; RV32IZFINX-NEXT: # %bb.1: # %if.end
1011-
; RV32IZFINX-NEXT: fmv.s a0, zero
1011+
; RV32IZFINX-NEXT: li a0, 0
10121012
; RV32IZFINX-NEXT: call dummy
10131013
; RV32IZFINX-NEXT: feq.s a0, a0, zero
10141014
; RV32IZFINX-NEXT: beqz a0, .LBB17_3
@@ -1024,12 +1024,12 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
10241024
; RV64IZFINX: # %bb.0: # %entry
10251025
; RV64IZFINX-NEXT: addi sp, sp, -16
10261026
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1027-
; RV64IZFINX-NEXT: fmv.s a0, zero
1027+
; RV64IZFINX-NEXT: li a0, 0
10281028
; RV64IZFINX-NEXT: call dummy
10291029
; RV64IZFINX-NEXT: feq.s a0, a0, zero
10301030
; RV64IZFINX-NEXT: beqz a0, .LBB17_3
10311031
; RV64IZFINX-NEXT: # %bb.1: # %if.end
1032-
; RV64IZFINX-NEXT: fmv.s a0, zero
1032+
; RV64IZFINX-NEXT: li a0, 0
10331033
; RV64IZFINX-NEXT: call dummy
10341034
; RV64IZFINX-NEXT: feq.s a0, a0, zero
10351035
; RV64IZFINX-NEXT: beqz a0, .LBB17_3

‎llvm/test/CodeGen/RISCV/float-convert.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -671,10 +671,10 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
671671
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
672672
; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
673673
; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
674-
; RV32IZFINX-NEXT: fmv.s s0, a0
674+
; RV32IZFINX-NEXT: mv s0, a0
675675
; RV32IZFINX-NEXT: lui a0, 913408
676676
; RV32IZFINX-NEXT: fle.s s1, a0, s0
677-
; RV32IZFINX-NEXT: fmv.s a0, s0
677+
; RV32IZFINX-NEXT: mv a0, s0
678678
; RV32IZFINX-NEXT: call __fixsfdi
679679
; RV32IZFINX-NEXT: lui a4, 524288
680680
; RV32IZFINX-NEXT: lui a2, 524288
@@ -905,10 +905,10 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
905905
; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
906906
; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
907907
; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
908-
; RV32IZFINX-NEXT: fmv.s s0, a0
908+
; RV32IZFINX-NEXT: mv s0, a0
909909
; RV32IZFINX-NEXT: fle.s a0, zero, a0
910910
; RV32IZFINX-NEXT: neg s1, a0
911-
; RV32IZFINX-NEXT: fmv.s a0, s0
911+
; RV32IZFINX-NEXT: mv a0, s0
912912
; RV32IZFINX-NEXT: call __fixunssfdi
913913
; RV32IZFINX-NEXT: and a0, s1, a0
914914
; RV32IZFINX-NEXT: lui a2, 391168

‎llvm/test/CodeGen/RISCV/float-imm.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ define float @float_positive_zero(ptr %pf) nounwind {
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;
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; CHECKZFINX-LABEL: float_positive_zero:
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; CHECKZFINX: # %bb.0:
60-
; CHECKZFINX-NEXT: fmv.s a0, zero
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; CHECKZFINX-NEXT: li a0, 0
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; CHECKZFINX-NEXT: ret
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ret float 0.0
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}

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