Don't sink splat operands when VT is scalable

Author: hazzlim

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

@@ -5240,6 +5240,10 @@ bool AArch64TTIImpl::isProfitableToSinkOperands(
     return !Ops.empty() && (NumSExts == 2 || NumZExts == 2);
   }
   case Instruction::FMul: {
+    // For SVE the lane-indexing is within 128-bits, so we can't fold splats.
+    if (I->getType()->isScalableTy())
+      return false;
+
     // Sink splats for index lane variants
     if (isSplatShuffle(I->getOperand(0)))
       Ops.push_back(&I->getOperandUse(0));

llvm/test/CodeGen/AArch64/sinksplat.ll

@@ -426,13 +426,12 @@ l2:
 define <vscale x 4 x float> @fmul_scalable(ptr %x, ptr %y) {
 ; CHECK-LABEL: fmul_scalable:
 ; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    rdvl x8, #1
-; CHECK-NEXT:    ldr s1, [x0]
 ; CHECK-NEXT:    mov z0.s, #0 // =0x0
 ; CHECK-NEXT:    sxtw x8, w8
-; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    mov w9, #1 // =0x1
-; CHECK-NEXT:    mov z1.s, s1
+; CHECK-NEXT:    ld1rw { z1.s }, p0/z, [x0]
 ; CHECK-NEXT:    lsl x8, x8, #2
 ; CHECK-NEXT:  .LBB13_1: // %l1
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1