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[RISCV] Add missing RISCVMaskedPseudo on some RVV memory ops
So that we can turn masked operations with all-ones masks into their unmasked counterpart.
1 parent 0c7d722 commit 4ad7a62

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9 files changed

+51
-101
lines changed

9 files changed

+51
-101
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3791,13 +3791,14 @@ static bool isImplicitDef(SDValue V) {
37913791
return V.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
37923792
}
37933793

3794-
static bool hasGPROut(unsigned Opc) {
3795-
switch (RISCV::getRVVMCOpcode(Opc)) {
3794+
static bool hasPassthru(const MCInstrDesc &MCID) {
3795+
switch (RISCV::getRVVMCOpcode(MCID.getOpcode())) {
37963796
case RISCV::VCPOP_M:
37973797
case RISCV::VFIRST_M:
3798-
return true;
3798+
return false;
37993799
}
3800-
return false;
3800+
// None of the stores has passthru.
3801+
return !MCID.mayStore();
38013802
}
38023803

38033804
// Optimize masked RVV pseudo instructions with a known all-ones mask to their
@@ -3829,8 +3830,9 @@ bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(MachineSDNode *N) {
38293830
#endif
38303831

38313832
SmallVector<SDValue, 8> Ops;
3832-
// Skip the passthru operand at index 0 if !UseTUPseudo and no GPR out.
3833-
bool ShouldSkip = !UseTUPseudo && !hasGPROut(Opc);
3833+
// Skip the passthru operand at index 0 if !UseTUPseudo and has the passthru
3834+
// operand.
3835+
bool ShouldSkip = !UseTUPseudo && hasPassthru(MCID);
38343836
for (unsigned I = ShouldSkip, E = N->getNumOperands(); I != E; I++) {
38353837
// Skip the mask, and the Glue.
38363838
SDValue Op = N->getOperand(I);

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1932,6 +1932,7 @@ multiclass VPseudoUSStore {
19321932
def "E" # eew # "_V_" # LInfo : VPseudoUSStoreNoMask<vreg, eew>,
19331933
VSESched<LInfo>;
19341934
def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSStoreMask<vreg, eew>,
1935+
RISCVMaskedPseudo<MaskIdx=2>,
19351936
VSESched<LInfo>;
19361937
}
19371938
}
@@ -1958,6 +1959,7 @@ multiclass VPseudoSStore {
19581959
def "E" # eew # "_V_" # LInfo : VPseudoSStoreNoMask<vreg, eew>,
19591960
VSSSched<eew, LInfo>;
19601961
def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSStoreMask<vreg, eew>,
1962+
RISCVMaskedPseudo<MaskIdx=3>,
19611963
VSSSched<eew, LInfo>;
19621964
}
19631965
}
@@ -1984,6 +1986,7 @@ multiclass VPseudoIStore<bit Ordered> {
19841986
VSXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
19851987
def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
19861988
VPseudoIStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
1989+
RISCVMaskedPseudo<MaskIdx=3>,
19871990
VSXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
19881991
}
19891992
}
@@ -3709,7 +3712,8 @@ multiclass VPseudoUSSegLoad {
37093712
def nf # "E" # eew # "_V_" # LInfo :
37103713
VPseudoUSSegLoadNoMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
37113714
def nf # "E" # eew # "_V_" # LInfo # "_MASK" :
3712-
VPseudoUSSegLoadMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
3715+
VPseudoUSSegLoadMask<vreg, eew, nf>, RISCVMaskedPseudo<MaskIdx=2>,
3716+
VLSEGSched<nf, eew, LInfo>;
37133717
}
37143718
}
37153719
}
@@ -3726,7 +3730,8 @@ multiclass VPseudoUSSegLoadFF {
37263730
def nf # "E" # eew # "FF_V_" # LInfo :
37273731
VPseudoUSSegLoadFFNoMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
37283732
def nf # "E" # eew # "FF_V_" # LInfo # "_MASK" :
3729-
VPseudoUSSegLoadFFMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
3733+
VPseudoUSSegLoadFFMask<vreg, eew, nf>, RISCVMaskedPseudo<MaskIdx=2>,
3734+
VLSEGFFSched<nf, eew, LInfo>;
37303735
}
37313736
}
37323737
}
@@ -3743,6 +3748,7 @@ multiclass VPseudoSSegLoad {
37433748
def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegLoadNoMask<vreg, eew, nf>,
37443749
VLSSEGSched<nf, eew, LInfo>;
37453750
def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegLoadMask<vreg, eew, nf>,
3751+
RISCVMaskedPseudo<MaskIdx=3>,
37463752
VLSSEGSched<nf, eew, LInfo>;
37473753
}
37483754
}
@@ -3773,6 +3779,7 @@ multiclass VPseudoISegLoad<bit Ordered> {
37733779
def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
37743780
VPseudoISegLoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
37753781
nf, Ordered>,
3782+
RISCVMaskedPseudo<MaskIdx=3>,
37763783
VLXSEGSched<nf, dataEEW, Ordered, DataLInfo>;
37773784
}
37783785
}
@@ -3792,6 +3799,7 @@ multiclass VPseudoUSSegStore {
37923799
def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegStoreNoMask<vreg, eew, nf>,
37933800
VSSEGSched<nf, eew, LInfo>;
37943801
def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSSegStoreMask<vreg, eew, nf>,
3802+
RISCVMaskedPseudo<MaskIdx=2>,
37953803
VSSEGSched<nf, eew, LInfo>;
37963804
}
37973805
}
@@ -3809,6 +3817,7 @@ multiclass VPseudoSSegStore {
38093817
def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegStoreNoMask<vreg, eew, nf>,
38103818
VSSSEGSched<nf, eew, LInfo>;
38113819
def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegStoreMask<vreg, eew, nf>,
3820+
RISCVMaskedPseudo<MaskIdx=3>,
38123821
VSSSEGSched<nf, eew, LInfo>;
38133822
}
38143823
}
@@ -3839,6 +3848,7 @@ multiclass VPseudoISegStore<bit Ordered> {
38393848
def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
38403849
VPseudoISegStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
38413850
nf, Ordered>,
3851+
RISCVMaskedPseudo<MaskIdx=3>,
38423852
VSXSEGSched<nf, idxEEW, Ordered, DataLInfo>;
38433853
}
38443854
}

‎llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll‎

Lines changed: 7 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -32,10 +32,8 @@ entry:
3232
define <vscale x 1 x i8> @test_vlseg2_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_2t(ptr %base, i64 %vl) {
3333
; CHECK-LABEL: test_vlseg2_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_2t:
3434
; CHECK: # %bb.0: # %entry
35-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
36-
; CHECK-NEXT: vmset.m v0
3735
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
38-
; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t
36+
; CHECK-NEXT: vlseg2e8.v v7, (a0)
3937
; CHECK-NEXT: ret
4038
entry:
4139
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) undef, ptr %base, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 1, i64 3)
@@ -208,10 +206,8 @@ entry:
208206
define <vscale x 1 x i8> @test_vlseg3_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_3t(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) {
209207
; CHECK-LABEL: test_vlseg3_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_3t:
210208
; CHECK: # %bb.0: # %entry
211-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
212-
; CHECK-NEXT: vmset.m v0
213209
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
214-
; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t
210+
; CHECK-NEXT: vlseg3e8.v v7, (a0)
215211
; CHECK-NEXT: ret
216212
entry:
217213
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) undef, ptr %base, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 1, i64 3)
@@ -357,10 +353,8 @@ entry:
357353
define <vscale x 1 x i8> @test_vlseg4_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_4t(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) {
358354
; CHECK-LABEL: test_vlseg4_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_4t:
359355
; CHECK: # %bb.0: # %entry
360-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
361-
; CHECK-NEXT: vmset.m v0
362356
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
363-
; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t
357+
; CHECK-NEXT: vlseg4e8.v v7, (a0)
364358
; CHECK-NEXT: ret
365359
entry:
366360
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) undef, ptr %base, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 1, i64 3)
@@ -506,10 +500,8 @@ entry:
506500
define <vscale x 1 x i8> @test_vlseg5_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_5t(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) {
507501
; CHECK-LABEL: test_vlseg5_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_5t:
508502
; CHECK: # %bb.0: # %entry
509-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
510-
; CHECK-NEXT: vmset.m v0
511503
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
512-
; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t
504+
; CHECK-NEXT: vlseg5e8.v v7, (a0)
513505
; CHECK-NEXT: ret
514506
entry:
515507
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) undef, ptr %base, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 1, i64 3)
@@ -628,10 +620,8 @@ entry:
628620
define <vscale x 1 x i8> @test_vlseg6_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_6t(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) {
629621
; CHECK-LABEL: test_vlseg6_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_6t:
630622
; CHECK: # %bb.0: # %entry
631-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
632-
; CHECK-NEXT: vmset.m v0
633623
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
634-
; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t
624+
; CHECK-NEXT: vlseg6e8.v v7, (a0)
635625
; CHECK-NEXT: ret
636626
entry:
637627
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) undef, ptr %base, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 1, i64 3)
@@ -750,10 +740,8 @@ entry:
750740
define <vscale x 1 x i8> @test_vlseg7_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_7t(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) {
751741
; CHECK-LABEL: test_vlseg7_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_7t:
752742
; CHECK: # %bb.0: # %entry
753-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
754-
; CHECK-NEXT: vmset.m v0
755743
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
756-
; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t
744+
; CHECK-NEXT: vlseg7e8.v v7, (a0)
757745
; CHECK-NEXT: ret
758746
entry:
759747
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) undef, ptr %base, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 1, i64 3)
@@ -872,10 +860,8 @@ entry:
872860
define <vscale x 1 x i8> @test_vlseg8_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_8t(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) {
873861
; CHECK-LABEL: test_vlseg8_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_8t:
874862
; CHECK: # %bb.0: # %entry
875-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
876-
; CHECK-NEXT: vmset.m v0
877863
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
878-
; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t
864+
; CHECK-NEXT: vlseg8e8.v v7, (a0)
879865
; CHECK-NEXT: ret
880866
entry:
881867
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) undef, ptr %base, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 1, i64 3)

‎llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll‎

Lines changed: 7 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -34,10 +34,8 @@ entry:
3434
define <vscale x 1 x i8> @test_vluxseg2_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i8(ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
3535
; CHECK-LABEL: test_vluxseg2_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i8:
3636
; CHECK: # %bb.0: # %entry
37-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
38-
; CHECK-NEXT: vmset.m v0
3937
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
40-
; CHECK-NEXT: vluxseg2ei8.v v9, (a0), v8, v0.t
38+
; CHECK-NEXT: vluxseg2ei8.v v9, (a0), v8
4139
; CHECK-NEXT: vmv1r.v v8, v10
4240
; CHECK-NEXT: ret
4341
entry:
@@ -658,10 +656,8 @@ entry:
658656
define <vscale x 1 x i8> @test_vluxseg3_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i8(ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
659657
; CHECK-LABEL: test_vluxseg3_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i8:
660658
; CHECK: # %bb.0: # %entry
661-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
662-
; CHECK-NEXT: vmset.m v0
663659
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
664-
; CHECK-NEXT: vluxseg3ei8.v v9, (a0), v8, v0.t
660+
; CHECK-NEXT: vluxseg3ei8.v v9, (a0), v8
665661
; CHECK-NEXT: vmv1r.v v8, v10
666662
; CHECK-NEXT: ret
667663
entry:
@@ -1224,10 +1220,8 @@ entry:
12241220
define <vscale x 1 x i8> @test_vluxseg4_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i8(ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
12251221
; CHECK-LABEL: test_vluxseg4_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i8:
12261222
; CHECK: # %bb.0: # %entry
1227-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
1228-
; CHECK-NEXT: vmset.m v0
12291223
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
1230-
; CHECK-NEXT: vluxseg4ei8.v v9, (a0), v8, v0.t
1224+
; CHECK-NEXT: vluxseg4ei8.v v9, (a0), v8
12311225
; CHECK-NEXT: vmv1r.v v8, v10
12321226
; CHECK-NEXT: ret
12331227
entry:
@@ -1790,10 +1784,8 @@ entry:
17901784
define <vscale x 1 x i8> @test_vluxseg5_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i8(ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
17911785
; CHECK-LABEL: test_vluxseg5_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i8:
17921786
; CHECK: # %bb.0: # %entry
1793-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
1794-
; CHECK-NEXT: vmset.m v0
17951787
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
1796-
; CHECK-NEXT: vluxseg5ei8.v v9, (a0), v8, v0.t
1788+
; CHECK-NEXT: vluxseg5ei8.v v9, (a0), v8
17971789
; CHECK-NEXT: vmv1r.v v8, v10
17981790
; CHECK-NEXT: ret
17991791
entry:
@@ -2269,10 +2261,8 @@ entry:
22692261
define <vscale x 1 x i8> @test_vluxseg6_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i8(ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
22702262
; CHECK-LABEL: test_vluxseg6_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i8:
22712263
; CHECK: # %bb.0: # %entry
2272-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
2273-
; CHECK-NEXT: vmset.m v0
22742264
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
2275-
; CHECK-NEXT: vluxseg6ei8.v v9, (a0), v8, v0.t
2265+
; CHECK-NEXT: vluxseg6ei8.v v9, (a0), v8
22762266
; CHECK-NEXT: vmv1r.v v8, v10
22772267
; CHECK-NEXT: ret
22782268
entry:
@@ -2748,10 +2738,8 @@ entry:
27482738
define <vscale x 1 x i8> @test_vluxseg7_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i8(ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
27492739
; CHECK-LABEL: test_vluxseg7_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i8:
27502740
; CHECK: # %bb.0: # %entry
2751-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
2752-
; CHECK-NEXT: vmset.m v0
27532741
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
2754-
; CHECK-NEXT: vluxseg7ei8.v v9, (a0), v8, v0.t
2742+
; CHECK-NEXT: vluxseg7ei8.v v9, (a0), v8
27552743
; CHECK-NEXT: vmv1r.v v8, v10
27562744
; CHECK-NEXT: ret
27572745
entry:
@@ -3227,10 +3215,8 @@ entry:
32273215
define <vscale x 1 x i8> @test_vluxseg8_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i8(ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {
32283216
; CHECK-LABEL: test_vluxseg8_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i8:
32293217
; CHECK: # %bb.0: # %entry
3230-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
3231-
; CHECK-NEXT: vmset.m v0
32323218
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
3233-
; CHECK-NEXT: vluxseg8ei8.v v9, (a0), v8, v0.t
3219+
; CHECK-NEXT: vluxseg8ei8.v v9, (a0), v8
32343220
; CHECK-NEXT: vmv1r.v v8, v10
32353221
; CHECK-NEXT: ret
32363222
entry:

‎llvm/test/CodeGen/RISCV/rvv/vse.ll‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -49,10 +49,8 @@ entry:
4949
define void @intrinsic_vse_allonesmask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
5050
; CHECK-LABEL: intrinsic_vse_allonesmask_v_nxv1i64_nxv1i64:
5151
; CHECK: # %bb.0: # %entry
52-
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
53-
; CHECK-NEXT: vmset.m v0
5452
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
55-
; CHECK-NEXT: vse64.v v8, (a0), v0.t
53+
; CHECK-NEXT: vse64.v v8, (a0)
5654
; CHECK-NEXT: ret
5755
entry:
5856
call void @llvm.riscv.vse.mask.nxv1i64(

‎llvm/test/CodeGen/RISCV/rvv/vsse.ll‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -53,10 +53,8 @@ entry:
5353
define void @intrinsic_vsse_allonesmask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
5454
; CHECK-LABEL: intrinsic_vsse_allonesmask_v_nxv1i64_nxv1i64:
5555
; CHECK: # %bb.0: # %entry
56-
; CHECK-NEXT: vsetvli a3, zero, e8, mf8, ta, ma
57-
; CHECK-NEXT: vmset.m v0
5856
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma
59-
; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t
57+
; CHECK-NEXT: vsse64.v v8, (a0), a1
6058
; CHECK-NEXT: ret
6159
entry:
6260
call void @llvm.riscv.vsse.mask.nxv1i64(

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