@@ -462,10 +462,6 @@ class SIGfx90ACacheControl : public SIGfx7CacheControl {
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SIAtomicScope Scope,
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SIAtomicAddrSpace AddrSpace) const override ;
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- bool enableStoreCacheBypass (const MachineBasicBlock::iterator &MI,
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- SIAtomicScope Scope,
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- SIAtomicAddrSpace AddrSpace) const override ;
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-
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bool enableRMWCacheBypass (const MachineBasicBlock::iterator &MI,
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SIAtomicScope Scope,
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SIAtomicAddrSpace AddrSpace) const override ;
@@ -1375,41 +1371,6 @@ bool SIGfx90ACacheControl::enableLoadCacheBypass(
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return Changed;
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}
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- bool SIGfx90ACacheControl::enableStoreCacheBypass (
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- const MachineBasicBlock::iterator &MI,
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- SIAtomicScope Scope,
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- SIAtomicAddrSpace AddrSpace) const {
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- assert (!MI->mayLoad () && MI->mayStore ());
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- bool Changed = false ;
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-
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- if ((AddrSpace & SIAtomicAddrSpace::GLOBAL) != SIAtomicAddrSpace::NONE) {
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- switch (Scope) {
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- case SIAtomicScope::SYSTEM:
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- case SIAtomicScope::AGENT:
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- // / Do not set glc for store atomic operations as they implicitly write
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- // / through the L1 cache.
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- break ;
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- case SIAtomicScope::WORKGROUP:
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- case SIAtomicScope::WAVEFRONT:
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- case SIAtomicScope::SINGLETHREAD:
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- // No cache to bypass. Store atomics implicitly write through the L1
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- // cache.
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- break ;
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- default :
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- llvm_unreachable (" Unsupported synchronization scope" );
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- }
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- }
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-
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- // / The scratch address space does not need the global memory caches
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- // / to be bypassed as all memory operations by the same thread are
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- // / sequentially consistent, and no other thread can access scratch
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- // / memory.
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-
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- // / Other address spaces do not have a cache.
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-
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- return Changed;
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- }
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-
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bool SIGfx90ACacheControl::enableRMWCacheBypass (
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const MachineBasicBlock::iterator &MI,
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SIAtomicScope Scope,
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