fixup! [RISCV] Update to Xqciint v0.4

lenary · lenary · commit 4b39e6f39f56 · 2025-03-06T17:36:48.000-08:00
diff --git a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
@@ -100,7 +100,8 @@ RISCVMachineFunctionInfo::getPushPopKind(const MachineFunction &MF) const {
   return PushPopKind::None;
 }
 
-bool RISCVMachineFunctionInfo::hasImplicitFPUpdates(const MachineFunction &MF) const {
+bool RISCVMachineFunctionInfo::hasImplicitFPUpdates(
+    const MachineFunction &MF) const {
   switch (getInterruptStackKind(MF)) {
   case InterruptStackKind::QCINest:
   case InterruptStackKind::QCINoNest:
@@ -122,7 +123,6 @@ bool RISCVMachineFunctionInfo::hasImplicitFPUpdates(const MachineFunction &MF) c
   return false;
 }
 
-
 void RISCVMachineFunctionInfo::initializeBaseYamlFields(
     const yaml::RISCVMachineFunctionInfo &YamlMFI) {
   VarArgsFrameIndex = YamlMFI.VarArgsFrameIndex;
@@ -136,4 +136,3 @@ void RISCVMachineFunctionInfo::addSExt32Register(Register Reg) {
 bool RISCVMachineFunctionInfo::isSExt32Register(Register Reg) const {
   return is_contained(SExt32Registers, Reg);
 }
-

Original file line number	Diff line number	Diff line change
`@@ -100,7 +100,8 @@ RISCVMachineFunctionInfo::getPushPopKind(const MachineFunction &MF) const {`
`100`	`100`	`return PushPopKind::None;`
`101`	`101`	`}`
`102`	`102`
`103`		`-bool RISCVMachineFunctionInfo::hasImplicitFPUpdates(const MachineFunction &MF) const {`
	`103`	`+bool RISCVMachineFunctionInfo::hasImplicitFPUpdates(`
	`104`	`+ const MachineFunction &MF) const {`
`104`	`105`	`switch (getInterruptStackKind(MF)) {`
`105`	`106`	`case InterruptStackKind::QCINest:`
`106`	`107`	`case InterruptStackKind::QCINoNest:`
`@@ -122,7 +123,6 @@ bool RISCVMachineFunctionInfo::hasImplicitFPUpdates(const MachineFunction &MF) c`
`122`	`123`	`return false;`
`123`	`124`	`}`
`124`	`125`
`125`		`-`
`126`	`126`	`void RISCVMachineFunctionInfo::initializeBaseYamlFields(`
`127`	`127`	`const yaml::RISCVMachineFunctionInfo &YamlMFI) {`
`128`	`128`	`VarArgsFrameIndex = YamlMFI.VarArgsFrameIndex;`
`@@ -136,4 +136,3 @@ void RISCVMachineFunctionInfo::addSExt32Register(Register Reg) {`
`136`	`136`	`bool RISCVMachineFunctionInfo::isSExt32Register(Register Reg) const {`
`137`	`137`	`return is_contained(SExt32Registers, Reg);`
`138`	`138`	`}`
`139`		`-`