Fix again

Author: svs-quic

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -16079,7 +16079,7 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG,
   uint64_t MulAmt = CNode->getZExtValue();
 
   // Don't do this if the Xqciac extension is enabled and the MulAmt in simm12.
-  if (Subtarget.hasVendorXqciac() && isInt<12>(MulAmt))
+  if (Subtarget.hasVendorXqciac() && isInt<12>(CNode->getSExtValue()))
     return SDValue();
 
   const bool HasShlAdd = Subtarget.hasStdExtZba() ||

llvm/test/CodeGen/RISCV/xqciac.ll

@@ -464,7 +464,7 @@ entry:
   ret i32 %add
 }
 
-define i32 @testmuliaddnegimm(i32 %a, i32 %b) {
+define i32 @testmuliaddnegimm(i32 %a) {
 ; RV32IM-LABEL: testmuliaddnegimm:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    slli a1, a0, 1
@@ -482,6 +482,9 @@ define i32 @testmuliaddnegimm(i32 %a, i32 %b) {
 ;
 ; RV32IZBAMXQCIAC-LABEL: testmuliaddnegimm:
 ; RV32IZBAMXQCIAC:       # %bb.0:
+; RV32IZBAMXQCIAC-NEXT:    li a1, 3
+; RV32IZBAMXQCIAC-NEXT:    qc.muliadd a1, a0, -3
+; RV32IZBAMXQCIAC-NEXT:    mv a0, a1
 ; RV32IZBAMXQCIAC-NEXT:    ret
   %mul = mul i32 %a, -3
   %add = add i32 %mul, 3