Skip to content

Commit 4be2975

Browse files
topperctopperc
authored
[RISCV][GISel] Support Zalasr (#161774)
We need additional patterns for GISel because we make s16 and s32 legal for load/store. GISel does not distinquish integer and FP scalar types in LLT. We only know whether the load should be integer or FP after register bank selection.
1 parent 435d084 commit 4be2975

File tree

3 files changed

+249
-5
lines changed

3 files changed

+249
-5
lines changed

‎llvm/lib/Target/RISCV/RISCVGISel.td‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -190,3 +190,29 @@ let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV64] in {
190190
def : Pat<(i64 (zext (i16 GPR:$rs))), (PACKW GPR:$rs, (XLenVT X0))>;
191191
def : Pat<(i32 (zext (i16 GPR:$rs))), (PACKW GPR:$rs, (XLenVT X0))>;
192192
}
193+
194+
//===----------------------------------------------------------------------===//
195+
// Zalasr patterns not used by SelectionDAG
196+
//===----------------------------------------------------------------------===//
197+
198+
let Predicates = [HasStdExtZalasr] in {
199+
// the sequentially consistent loads use
200+
// .aq instead of .aqrl to match the psABI/A.7
201+
def : PatLAQ<acquiring_load<atomic_load_aext_8>, LB_AQ, i16>;
202+
def : PatLAQ<seq_cst_load<atomic_load_aext_8>, LB_AQ, i16>;
203+
204+
def : PatLAQ<acquiring_load<atomic_load_nonext_16>, LH_AQ, i16>;
205+
def : PatLAQ<seq_cst_load<atomic_load_nonext_16>, LH_AQ, i16>;
206+
207+
def : PatSRL<releasing_store<atomic_store_8>, SB_RL, i16>;
208+
def : PatSRL<seq_cst_store<atomic_store_8>, SB_RL, i16>;
209+
210+
def : PatSRL<releasing_store<atomic_store_16>, SH_RL, i16>;
211+
def : PatSRL<seq_cst_store<atomic_store_16>, SH_RL, i16>;
212+
}
213+
214+
let Predicates = [HasStdExtZalasr, IsRV64] in {
215+
// Load pattern is in RISCVInstrInfoZalasr.td and shared with RV32.
216+
def : PatSRL<releasing_store<atomic_store_32>, SW_RL, i32>;
217+
def : PatSRL<seq_cst_store<atomic_store_32>, SW_RL, i32>;
218+
}

‎llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -93,12 +93,11 @@ let Predicates = [HasStdExtZalasr] in {
9393

9494
def : PatSRL<releasing_store<atomic_store_32>, SW_RL>;
9595
def : PatSRL<seq_cst_store<atomic_store_32>, SW_RL>;
96-
} // Predicates = [HasStdExtZalasr]
9796

98-
let Predicates = [HasStdExtZalasr, IsRV32] in {
99-
def : PatLAQ<acquiring_load<atomic_load_nonext_32>, LW_AQ>;
100-
def : PatLAQ<seq_cst_load<atomic_load_nonext_32>, LW_AQ>;
101-
} // Predicates = [HasStdExtZalasr, IsRV32]
97+
// Used by GISel for RV32 and RV64.
98+
def : PatLAQ<acquiring_load<atomic_load_nonext_32>, LW_AQ, i32>;
99+
def : PatLAQ<seq_cst_load<atomic_load_nonext_32>, LW_AQ, i32>;
100+
} // Predicates = [HasStdExtZalasr]
102101

103102
let Predicates = [HasStdExtZalasr, IsRV64] in {
104103
def : PatLAQ<acquiring_load<atomic_load_asext_32>, LW_AQ, i64>;

‎llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store.ll‎

Lines changed: 219 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,15 @@
2323
; RUN: llc -mtriple=riscv64 -global-isel -mattr=+a,+ztso -verify-machineinstrs < %s \
2424
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO-TRAILING-FENCE %s
2525

26+
; RUN: llc -mtriple=riscv32 -global-isel -mattr=+a,+experimental-zalasr -verify-machineinstrs < %s \
27+
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-WMO %s
28+
; RUN: llc -mtriple=riscv32 -global-isel -mattr=+a,+experimental-zalasr,+ztso -verify-machineinstrs < %s \
29+
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-TSO %s
30+
31+
; RUN: llc -mtriple=riscv64 -global-isel -mattr=+a,+experimental-zalasr -verify-machineinstrs < %s \
32+
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZALASR,RV64IA-ZALASR-WMO %s
33+
; RUN: llc -mtriple=riscv64 -global-isel -mattr=+a,+experimental-zalasr,+ztso -verify-machineinstrs < %s \
34+
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZALASR,RV64IA-ZALASR-TSO %s
2635

2736
define i8 @atomic_load_i8_unordered(ptr %a) nounwind {
2837
; RV32I-LABEL: atomic_load_i8_unordered:
@@ -156,6 +165,26 @@ define i8 @atomic_load_i8_acquire(ptr %a) nounwind {
156165
; RV64IA-TSO-TRAILING-FENCE: # %bb.0:
157166
; RV64IA-TSO-TRAILING-FENCE-NEXT: lbu a0, 0(a0)
158167
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
168+
;
169+
; RV32IA-ZALASR-WMO-LABEL: atomic_load_i8_acquire:
170+
; RV32IA-ZALASR-WMO: # %bb.0:
171+
; RV32IA-ZALASR-WMO-NEXT: lb.aq a0, (a0)
172+
; RV32IA-ZALASR-WMO-NEXT: ret
173+
;
174+
; RV32IA-ZALASR-TSO-LABEL: atomic_load_i8_acquire:
175+
; RV32IA-ZALASR-TSO: # %bb.0:
176+
; RV32IA-ZALASR-TSO-NEXT: lbu a0, 0(a0)
177+
; RV32IA-ZALASR-TSO-NEXT: ret
178+
;
179+
; RV64IA-ZALASR-WMO-LABEL: atomic_load_i8_acquire:
180+
; RV64IA-ZALASR-WMO: # %bb.0:
181+
; RV64IA-ZALASR-WMO-NEXT: lb.aq a0, (a0)
182+
; RV64IA-ZALASR-WMO-NEXT: ret
183+
;
184+
; RV64IA-ZALASR-TSO-LABEL: atomic_load_i8_acquire:
185+
; RV64IA-ZALASR-TSO: # %bb.0:
186+
; RV64IA-ZALASR-TSO-NEXT: lbu a0, 0(a0)
187+
; RV64IA-ZALASR-TSO-NEXT: ret
159188
%1 = load atomic i8, ptr %a acquire, align 1
160189
ret i8 %1
161190
}
@@ -232,6 +261,16 @@ define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind {
232261
; RV64IA-TSO-TRAILING-FENCE-NEXT: fence rw, rw
233262
; RV64IA-TSO-TRAILING-FENCE-NEXT: lbu a0, 0(a0)
234263
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
264+
;
265+
; RV32IA-ZALASR-LABEL: atomic_load_i8_seq_cst:
266+
; RV32IA-ZALASR: # %bb.0:
267+
; RV32IA-ZALASR-NEXT: lb.aq a0, (a0)
268+
; RV32IA-ZALASR-NEXT: ret
269+
;
270+
; RV64IA-ZALASR-LABEL: atomic_load_i8_seq_cst:
271+
; RV64IA-ZALASR: # %bb.0:
272+
; RV64IA-ZALASR-NEXT: lb.aq a0, (a0)
273+
; RV64IA-ZALASR-NEXT: ret
235274
%1 = load atomic i8, ptr %a seq_cst, align 1
236275
ret i8 %1
237276
}
@@ -368,6 +407,26 @@ define i16 @atomic_load_i16_acquire(ptr %a) nounwind {
368407
; RV64IA-TSO-TRAILING-FENCE: # %bb.0:
369408
; RV64IA-TSO-TRAILING-FENCE-NEXT: lh a0, 0(a0)
370409
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
410+
;
411+
; RV32IA-ZALASR-WMO-LABEL: atomic_load_i16_acquire:
412+
; RV32IA-ZALASR-WMO: # %bb.0:
413+
; RV32IA-ZALASR-WMO-NEXT: lh.aq a0, (a0)
414+
; RV32IA-ZALASR-WMO-NEXT: ret
415+
;
416+
; RV32IA-ZALASR-TSO-LABEL: atomic_load_i16_acquire:
417+
; RV32IA-ZALASR-TSO: # %bb.0:
418+
; RV32IA-ZALASR-TSO-NEXT: lh a0, 0(a0)
419+
; RV32IA-ZALASR-TSO-NEXT: ret
420+
;
421+
; RV64IA-ZALASR-WMO-LABEL: atomic_load_i16_acquire:
422+
; RV64IA-ZALASR-WMO: # %bb.0:
423+
; RV64IA-ZALASR-WMO-NEXT: lh.aq a0, (a0)
424+
; RV64IA-ZALASR-WMO-NEXT: ret
425+
;
426+
; RV64IA-ZALASR-TSO-LABEL: atomic_load_i16_acquire:
427+
; RV64IA-ZALASR-TSO: # %bb.0:
428+
; RV64IA-ZALASR-TSO-NEXT: lh a0, 0(a0)
429+
; RV64IA-ZALASR-TSO-NEXT: ret
371430
%1 = load atomic i16, ptr %a acquire, align 2
372431
ret i16 %1
373432
}
@@ -444,6 +503,16 @@ define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind {
444503
; RV64IA-TSO-TRAILING-FENCE-NEXT: fence rw, rw
445504
; RV64IA-TSO-TRAILING-FENCE-NEXT: lh a0, 0(a0)
446505
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
506+
;
507+
; RV32IA-ZALASR-LABEL: atomic_load_i16_seq_cst:
508+
; RV32IA-ZALASR: # %bb.0:
509+
; RV32IA-ZALASR-NEXT: lh.aq a0, (a0)
510+
; RV32IA-ZALASR-NEXT: ret
511+
;
512+
; RV64IA-ZALASR-LABEL: atomic_load_i16_seq_cst:
513+
; RV64IA-ZALASR: # %bb.0:
514+
; RV64IA-ZALASR-NEXT: lh.aq a0, (a0)
515+
; RV64IA-ZALASR-NEXT: ret
447516
%1 = load atomic i16, ptr %a seq_cst, align 2
448517
ret i16 %1
449518
}
@@ -580,6 +649,26 @@ define i32 @atomic_load_i32_acquire(ptr %a) nounwind {
580649
; RV64IA-TSO-TRAILING-FENCE: # %bb.0:
581650
; RV64IA-TSO-TRAILING-FENCE-NEXT: lw a0, 0(a0)
582651
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
652+
;
653+
; RV32IA-ZALASR-WMO-LABEL: atomic_load_i32_acquire:
654+
; RV32IA-ZALASR-WMO: # %bb.0:
655+
; RV32IA-ZALASR-WMO-NEXT: lw.aq a0, (a0)
656+
; RV32IA-ZALASR-WMO-NEXT: ret
657+
;
658+
; RV32IA-ZALASR-TSO-LABEL: atomic_load_i32_acquire:
659+
; RV32IA-ZALASR-TSO: # %bb.0:
660+
; RV32IA-ZALASR-TSO-NEXT: lw a0, 0(a0)
661+
; RV32IA-ZALASR-TSO-NEXT: ret
662+
;
663+
; RV64IA-ZALASR-WMO-LABEL: atomic_load_i32_acquire:
664+
; RV64IA-ZALASR-WMO: # %bb.0:
665+
; RV64IA-ZALASR-WMO-NEXT: lw.aq a0, (a0)
666+
; RV64IA-ZALASR-WMO-NEXT: ret
667+
;
668+
; RV64IA-ZALASR-TSO-LABEL: atomic_load_i32_acquire:
669+
; RV64IA-ZALASR-TSO: # %bb.0:
670+
; RV64IA-ZALASR-TSO-NEXT: lw a0, 0(a0)
671+
; RV64IA-ZALASR-TSO-NEXT: ret
583672
%1 = load atomic i32, ptr %a acquire, align 4
584673
ret i32 %1
585674
}
@@ -656,6 +745,16 @@ define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind {
656745
; RV64IA-TSO-TRAILING-FENCE-NEXT: fence rw, rw
657746
; RV64IA-TSO-TRAILING-FENCE-NEXT: lw a0, 0(a0)
658747
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
748+
;
749+
; RV32IA-ZALASR-LABEL: atomic_load_i32_seq_cst:
750+
; RV32IA-ZALASR: # %bb.0:
751+
; RV32IA-ZALASR-NEXT: lw.aq a0, (a0)
752+
; RV32IA-ZALASR-NEXT: ret
753+
;
754+
; RV64IA-ZALASR-LABEL: atomic_load_i32_seq_cst:
755+
; RV64IA-ZALASR: # %bb.0:
756+
; RV64IA-ZALASR-NEXT: lw.aq a0, (a0)
757+
; RV64IA-ZALASR-NEXT: ret
659758
%1 = load atomic i32, ptr %a seq_cst, align 4
660759
ret i32 %1
661760
}
@@ -790,6 +889,16 @@ define i64 @atomic_load_i64_acquire(ptr %a) nounwind {
790889
; RV64IA-TSO-TRAILING-FENCE: # %bb.0:
791890
; RV64IA-TSO-TRAILING-FENCE-NEXT: ld a0, 0(a0)
792891
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
892+
;
893+
; RV64IA-ZALASR-WMO-LABEL: atomic_load_i64_acquire:
894+
; RV64IA-ZALASR-WMO: # %bb.0:
895+
; RV64IA-ZALASR-WMO-NEXT: ld.aq a0, (a0)
896+
; RV64IA-ZALASR-WMO-NEXT: ret
897+
;
898+
; RV64IA-ZALASR-TSO-LABEL: atomic_load_i64_acquire:
899+
; RV64IA-ZALASR-TSO: # %bb.0:
900+
; RV64IA-ZALASR-TSO-NEXT: ld a0, 0(a0)
901+
; RV64IA-ZALASR-TSO-NEXT: ret
793902
%1 = load atomic i64, ptr %a acquire, align 8
794903
ret i64 %1
795904
}
@@ -850,6 +959,11 @@ define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind {
850959
; RV64IA-TSO-TRAILING-FENCE-NEXT: fence rw, rw
851960
; RV64IA-TSO-TRAILING-FENCE-NEXT: ld a0, 0(a0)
852961
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
962+
;
963+
; RV64IA-ZALASR-LABEL: atomic_load_i64_seq_cst:
964+
; RV64IA-ZALASR: # %bb.0:
965+
; RV64IA-ZALASR-NEXT: ld.aq a0, (a0)
966+
; RV64IA-ZALASR-NEXT: ret
853967
%1 = load atomic i64, ptr %a seq_cst, align 8
854968
ret i64 %1
855969
}
@@ -986,6 +1100,26 @@ define void @atomic_store_i8_release(ptr %a, i8 %b) nounwind {
9861100
; RV64IA-TSO-TRAILING-FENCE: # %bb.0:
9871101
; RV64IA-TSO-TRAILING-FENCE-NEXT: sb a1, 0(a0)
9881102
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
1103+
;
1104+
; RV32IA-ZALASR-WMO-LABEL: atomic_store_i8_release:
1105+
; RV32IA-ZALASR-WMO: # %bb.0:
1106+
; RV32IA-ZALASR-WMO-NEXT: sb.rl a1, (a0)
1107+
; RV32IA-ZALASR-WMO-NEXT: ret
1108+
;
1109+
; RV32IA-ZALASR-TSO-LABEL: atomic_store_i8_release:
1110+
; RV32IA-ZALASR-TSO: # %bb.0:
1111+
; RV32IA-ZALASR-TSO-NEXT: sb a1, 0(a0)
1112+
; RV32IA-ZALASR-TSO-NEXT: ret
1113+
;
1114+
; RV64IA-ZALASR-WMO-LABEL: atomic_store_i8_release:
1115+
; RV64IA-ZALASR-WMO: # %bb.0:
1116+
; RV64IA-ZALASR-WMO-NEXT: sb.rl a1, (a0)
1117+
; RV64IA-ZALASR-WMO-NEXT: ret
1118+
;
1119+
; RV64IA-ZALASR-TSO-LABEL: atomic_store_i8_release:
1120+
; RV64IA-ZALASR-TSO: # %bb.0:
1121+
; RV64IA-ZALASR-TSO-NEXT: sb a1, 0(a0)
1122+
; RV64IA-ZALASR-TSO-NEXT: ret
9891123
store atomic i8 %b, ptr %a release, align 1
9901124
ret void
9911125
}
@@ -1060,6 +1194,16 @@ define void @atomic_store_i8_seq_cst(ptr %a, i8 %b) nounwind {
10601194
; RV64IA-TSO-TRAILING-FENCE-NEXT: sb a1, 0(a0)
10611195
; RV64IA-TSO-TRAILING-FENCE-NEXT: fence rw, rw
10621196
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
1197+
;
1198+
; RV32IA-ZALASR-LABEL: atomic_store_i8_seq_cst:
1199+
; RV32IA-ZALASR: # %bb.0:
1200+
; RV32IA-ZALASR-NEXT: sb.rl a1, (a0)
1201+
; RV32IA-ZALASR-NEXT: ret
1202+
;
1203+
; RV64IA-ZALASR-LABEL: atomic_store_i8_seq_cst:
1204+
; RV64IA-ZALASR: # %bb.0:
1205+
; RV64IA-ZALASR-NEXT: sb.rl a1, (a0)
1206+
; RV64IA-ZALASR-NEXT: ret
10631207
store atomic i8 %b, ptr %a seq_cst, align 1
10641208
ret void
10651209
}
@@ -1196,6 +1340,26 @@ define void @atomic_store_i16_release(ptr %a, i16 %b) nounwind {
11961340
; RV64IA-TSO-TRAILING-FENCE: # %bb.0:
11971341
; RV64IA-TSO-TRAILING-FENCE-NEXT: sh a1, 0(a0)
11981342
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
1343+
;
1344+
; RV32IA-ZALASR-WMO-LABEL: atomic_store_i16_release:
1345+
; RV32IA-ZALASR-WMO: # %bb.0:
1346+
; RV32IA-ZALASR-WMO-NEXT: sh.rl a1, (a0)
1347+
; RV32IA-ZALASR-WMO-NEXT: ret
1348+
;
1349+
; RV32IA-ZALASR-TSO-LABEL: atomic_store_i16_release:
1350+
; RV32IA-ZALASR-TSO: # %bb.0:
1351+
; RV32IA-ZALASR-TSO-NEXT: sh a1, 0(a0)
1352+
; RV32IA-ZALASR-TSO-NEXT: ret
1353+
;
1354+
; RV64IA-ZALASR-WMO-LABEL: atomic_store_i16_release:
1355+
; RV64IA-ZALASR-WMO: # %bb.0:
1356+
; RV64IA-ZALASR-WMO-NEXT: sh.rl a1, (a0)
1357+
; RV64IA-ZALASR-WMO-NEXT: ret
1358+
;
1359+
; RV64IA-ZALASR-TSO-LABEL: atomic_store_i16_release:
1360+
; RV64IA-ZALASR-TSO: # %bb.0:
1361+
; RV64IA-ZALASR-TSO-NEXT: sh a1, 0(a0)
1362+
; RV64IA-ZALASR-TSO-NEXT: ret
11991363
store atomic i16 %b, ptr %a release, align 2
12001364
ret void
12011365
}
@@ -1270,6 +1434,16 @@ define void @atomic_store_i16_seq_cst(ptr %a, i16 %b) nounwind {
12701434
; RV64IA-TSO-TRAILING-FENCE-NEXT: sh a1, 0(a0)
12711435
; RV64IA-TSO-TRAILING-FENCE-NEXT: fence rw, rw
12721436
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
1437+
;
1438+
; RV32IA-ZALASR-LABEL: atomic_store_i16_seq_cst:
1439+
; RV32IA-ZALASR: # %bb.0:
1440+
; RV32IA-ZALASR-NEXT: sh.rl a1, (a0)
1441+
; RV32IA-ZALASR-NEXT: ret
1442+
;
1443+
; RV64IA-ZALASR-LABEL: atomic_store_i16_seq_cst:
1444+
; RV64IA-ZALASR: # %bb.0:
1445+
; RV64IA-ZALASR-NEXT: sh.rl a1, (a0)
1446+
; RV64IA-ZALASR-NEXT: ret
12731447
store atomic i16 %b, ptr %a seq_cst, align 2
12741448
ret void
12751449
}
@@ -1406,6 +1580,26 @@ define void @atomic_store_i32_release(ptr %a, i32 %b) nounwind {
14061580
; RV64IA-TSO-TRAILING-FENCE: # %bb.0:
14071581
; RV64IA-TSO-TRAILING-FENCE-NEXT: sw a1, 0(a0)
14081582
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
1583+
;
1584+
; RV32IA-ZALASR-WMO-LABEL: atomic_store_i32_release:
1585+
; RV32IA-ZALASR-WMO: # %bb.0:
1586+
; RV32IA-ZALASR-WMO-NEXT: sw.rl a1, (a0)
1587+
; RV32IA-ZALASR-WMO-NEXT: ret
1588+
;
1589+
; RV32IA-ZALASR-TSO-LABEL: atomic_store_i32_release:
1590+
; RV32IA-ZALASR-TSO: # %bb.0:
1591+
; RV32IA-ZALASR-TSO-NEXT: sw a1, 0(a0)
1592+
; RV32IA-ZALASR-TSO-NEXT: ret
1593+
;
1594+
; RV64IA-ZALASR-WMO-LABEL: atomic_store_i32_release:
1595+
; RV64IA-ZALASR-WMO: # %bb.0:
1596+
; RV64IA-ZALASR-WMO-NEXT: sw.rl a1, (a0)
1597+
; RV64IA-ZALASR-WMO-NEXT: ret
1598+
;
1599+
; RV64IA-ZALASR-TSO-LABEL: atomic_store_i32_release:
1600+
; RV64IA-ZALASR-TSO: # %bb.0:
1601+
; RV64IA-ZALASR-TSO-NEXT: sw a1, 0(a0)
1602+
; RV64IA-ZALASR-TSO-NEXT: ret
14091603
store atomic i32 %b, ptr %a release, align 4
14101604
ret void
14111605
}
@@ -1480,6 +1674,16 @@ define void @atomic_store_i32_seq_cst(ptr %a, i32 %b) nounwind {
14801674
; RV64IA-TSO-TRAILING-FENCE-NEXT: sw a1, 0(a0)
14811675
; RV64IA-TSO-TRAILING-FENCE-NEXT: fence rw, rw
14821676
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
1677+
;
1678+
; RV32IA-ZALASR-LABEL: atomic_store_i32_seq_cst:
1679+
; RV32IA-ZALASR: # %bb.0:
1680+
; RV32IA-ZALASR-NEXT: sw.rl a1, (a0)
1681+
; RV32IA-ZALASR-NEXT: ret
1682+
;
1683+
; RV64IA-ZALASR-LABEL: atomic_store_i32_seq_cst:
1684+
; RV64IA-ZALASR: # %bb.0:
1685+
; RV64IA-ZALASR-NEXT: sw.rl a1, (a0)
1686+
; RV64IA-ZALASR-NEXT: ret
14831687
store atomic i32 %b, ptr %a seq_cst, align 4
14841688
ret void
14851689
}
@@ -1614,6 +1818,16 @@ define void @atomic_store_i64_release(ptr %a, i64 %b) nounwind {
16141818
; RV64IA-TSO-TRAILING-FENCE: # %bb.0:
16151819
; RV64IA-TSO-TRAILING-FENCE-NEXT: sd a1, 0(a0)
16161820
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
1821+
;
1822+
; RV64IA-ZALASR-WMO-LABEL: atomic_store_i64_release:
1823+
; RV64IA-ZALASR-WMO: # %bb.0:
1824+
; RV64IA-ZALASR-WMO-NEXT: sd.rl a1, (a0)
1825+
; RV64IA-ZALASR-WMO-NEXT: ret
1826+
;
1827+
; RV64IA-ZALASR-TSO-LABEL: atomic_store_i64_release:
1828+
; RV64IA-ZALASR-TSO: # %bb.0:
1829+
; RV64IA-ZALASR-TSO-NEXT: sd a1, 0(a0)
1830+
; RV64IA-ZALASR-TSO-NEXT: ret
16171831
store atomic i64 %b, ptr %a release, align 8
16181832
ret void
16191833
}
@@ -1673,6 +1887,11 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %b) nounwind {
16731887
; RV64IA-TSO-TRAILING-FENCE-NEXT: sd a1, 0(a0)
16741888
; RV64IA-TSO-TRAILING-FENCE-NEXT: fence rw, rw
16751889
; RV64IA-TSO-TRAILING-FENCE-NEXT: ret
1890+
;
1891+
; RV64IA-ZALASR-LABEL: atomic_store_i64_seq_cst:
1892+
; RV64IA-ZALASR: # %bb.0:
1893+
; RV64IA-ZALASR-NEXT: sd.rl a1, (a0)
1894+
; RV64IA-ZALASR-NEXT: ret
16761895
store atomic i64 %b, ptr %a seq_cst, align 8
16771896
ret void
16781897
}

0 commit comments

Comments
 (0)