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1 parent b9c65be commit 4c5ce0dCopy full SHA for 4c5ce0d
clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
@@ -2006,9 +2006,8 @@ mlir::LogicalResult CIRToLLVMVecSplatOpLowering::matchAndRewrite(
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const mlir::Value oneElement = rewriter.create<mlir::LLVM::InsertElementOp>(
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loc, poison, elementValue, indexValue);
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const SmallVector<int32_t> zeroValues(vecTy.getSize(), 0);
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- const mlir::Value shuffled = rewriter.create<mlir::LLVM::ShuffleVectorOp>(
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- loc, oneElement, poison, zeroValues);
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- rewriter.replaceOp(op, shuffled);
+ rewriter.replaceOpWithNewOp<mlir::LLVM::ShuffleVectorOp>(op, oneElement,
+ poison, zeroValues);
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return mlir::success();
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}
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