Avoid hardcoding types and explicit constants

Signed-off-by: John Lu <[email protected]>

Author: LU-JOHN

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

@@ -4050,16 +4050,19 @@ SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
     // shl i64 X, Y -> [0, shl i32 X, (Y & 0x1F)]
     if (VT == MVT::i64) {
       KnownBits Known = DAG.computeKnownBits(RHS);
-      if (Known.getMinValue().getZExtValue() >= 32) {
-        SDValue truncShiftAmt = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, RHS);
-        const SDValue C31 = DAG.getConstant(31, SL, MVT::i32);
+      EVT TargetType=VT.getHalfSizedIntegerVT(*DAG.getContext());
+      EVT TargetVecPairType=EVT::getVectorVT(*DAG.getContext(), TargetType, 2);
+
+      if (Known.getMinValue().getZExtValue() >= TargetType.getSizeInBits()) {
+        SDValue truncShiftAmt = DAG.getNode(ISD::TRUNCATE, SL, TargetType, RHS);
+        const SDValue ShiftMask = DAG.getConstant(TargetType.getSizeInBits() - 1, SL, TargetType);
         SDValue MaskedShiftAmt =
-            DAG.getNode(ISD::AND, SL, MVT::i32, truncShiftAmt, C31);
-        SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
-        SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, MaskedShiftAmt);
-        const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
-        SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift});
-        return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
+            DAG.getNode(ISD::AND, SL, TargetType, truncShiftAmt, ShiftMask);
+        SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, TargetType, LHS);
+        SDValue NewShift = DAG.getNode(ISD::SHL, SL, TargetType, Lo, MaskedShiftAmt);
+        const SDValue Zero = DAG.getConstant(0, SL, TargetType);
+        SDValue Vec = DAG.getBuildVector(TargetVecPairType, SL, {Zero, NewShift});
+        return DAG.getNode(ISD::BITCAST, SL, VT, Vec);
       }
     }
     return SDValue();