[RISCV] Add coverage for shuffles which if widened could be zipeven/zipodd

Author: preames

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll

@@ -353,6 +353,49 @@ define <16 x i64> @zipodd_v16i64(<16 x i64> %v1, <16 x i64> %v2) {
   %out = shufflevector <16 x i64> %v1, <16 x i64> %v2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
   ret <16 x i64> %out
 }
+
+define <8 x i32> @zipeven_v8i32_as_v4i64(<8 x i32> %v1, <8 x i32> %v2) {
+; CHECK-LABEL: zipeven_v8i32_as_v4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 204
+; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
+; CHECK-NEXT:    vmv.s.x v0, a0
+; CHECK-NEXT:    vslideup.vi v8, v10, 2, v0.t
+; CHECK-NEXT:    ret
+;
+; ZIP-LABEL: zipeven_v8i32_as_v4i64:
+; ZIP:       # %bb.0:
+; ZIP-NEXT:    li a0, 204
+; ZIP-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
+; ZIP-NEXT:    vmv.s.x v0, a0
+; ZIP-NEXT:    vslideup.vi v8, v10, 2, v0.t
+; ZIP-NEXT:    ret
+  %out = shufflevector <8 x i32> %v1, <8 x i32> %v2, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 5, i32 12, i32 13>
+  ret <8 x i32> %out
+}
+
+define <8 x i32> @zipodd_v8i32_as_v4i64(<8 x i32> %v1, <8 x i32> %v2) {
+; CHECK-LABEL: zipodd_v8i32_as_v4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 51
+; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
+; CHECK-NEXT:    vmv.s.x v0, a0
+; CHECK-NEXT:    vslidedown.vi v10, v8, 2, v0.t
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
+;
+; ZIP-LABEL: zipodd_v8i32_as_v4i64:
+; ZIP:       # %bb.0:
+; ZIP-NEXT:    li a0, 51
+; ZIP-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
+; ZIP-NEXT:    vmv.s.x v0, a0
+; ZIP-NEXT:    vslidedown.vi v10, v8, 2, v0.t
+; ZIP-NEXT:    vmv.v.v v8, v10
+; ZIP-NEXT:    ret
+  %out = shufflevector <8 x i32> %v1, <8 x i32> %v2, <8 x i32> <i32 2, i32 3, i32 10, i32 11, i32 6, i32 7, i32 14, i32 15>
+  ret <8 x i32> %out
+}
+
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; RV32: {{.*}}
 ; RV64: {{.*}}