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[LoongArch][NFC] Pre-commit tests for combining and(not)
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‎llvm/test/CodeGen/LoongArch/lasx/and-not-combine.ll‎

Lines changed: 181 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2-
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
3-
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
2+
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
3+
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
44

55
define void @and_not_combine_v32i8(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
66
; CHECK-LABEL: and_not_combine_v32i8:
@@ -85,3 +85,182 @@ entry:
8585
store <4 x i64> %and, ptr %res
8686
ret void
8787
}
88+
89+
define void @pre_not_and_not_combine_v32i8(ptr %res, ptr %a, i8 %b) nounwind {
90+
; CHECK-LABEL: pre_not_and_not_combine_v32i8:
91+
; CHECK: # %bb.0:
92+
; CHECK-NEXT: xvld $xr0, $a1, 0
93+
; CHECK-NEXT: nor $a1, $a2, $zero
94+
; CHECK-NEXT: xvreplgr2vr.b $xr1, $a1
95+
; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr1
96+
; CHECK-NEXT: xvst $xr0, $a0, 0
97+
; CHECK-NEXT: ret
98+
%v0 = load <32 x i8>, ptr %a
99+
%b.not = xor i8 %b, -1
100+
%b.not.ele = insertelement <32 x i8> poison, i8 %b.not, i64 0
101+
%v1.not = shufflevector <32 x i8> %b.not.ele, <32 x i8> poison, <32 x i32> zeroinitializer
102+
%v0.not = xor <32 x i8> %v0, splat (i8 -1)
103+
%and = and <32 x i8> %v0.not, %v1.not
104+
store <32 x i8> %and, ptr %res
105+
ret void
106+
}
107+
108+
define void @post_not_and_not_combine_v32i8(ptr %res, ptr %a, i8 %b) nounwind {
109+
; CHECK-LABEL: post_not_and_not_combine_v32i8:
110+
; CHECK: # %bb.0:
111+
; CHECK-NEXT: xvld $xr0, $a1, 0
112+
; CHECK-NEXT: xvreplgr2vr.b $xr1, $a2
113+
; CHECK-NEXT: xvxori.b $xr1, $xr1, 255
114+
; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr1
115+
; CHECK-NEXT: xvst $xr0, $a0, 0
116+
; CHECK-NEXT: ret
117+
%v0 = load <32 x i8>, ptr %a
118+
%b.ele = insertelement <32 x i8> poison, i8 %b, i64 0
119+
%v1 = shufflevector <32 x i8> %b.ele, <32 x i8> poison, <32 x i32> zeroinitializer
120+
%v0.not = xor <32 x i8> %v0, splat (i8 -1)
121+
%v1.not = xor <32 x i8> %v1, splat (i8 -1)
122+
%and = and <32 x i8> %v0.not, %v1.not
123+
store <32 x i8> %and, ptr %res
124+
ret void
125+
}
126+
127+
define void @pre_not_and_not_combine_v16i16(ptr %res, ptr %a, i16 %b) nounwind {
128+
; CHECK-LABEL: pre_not_and_not_combine_v16i16:
129+
; CHECK: # %bb.0:
130+
; CHECK-NEXT: xvld $xr0, $a1, 0
131+
; CHECK-NEXT: nor $a1, $a2, $zero
132+
; CHECK-NEXT: xvreplgr2vr.h $xr1, $a1
133+
; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr1
134+
; CHECK-NEXT: xvst $xr0, $a0, 0
135+
; CHECK-NEXT: ret
136+
%v0 = load <16 x i16>, ptr %a
137+
%b.not = xor i16 %b, -1
138+
%b.not.ele = insertelement <16 x i16> poison, i16 %b.not, i64 0
139+
%v1.not = shufflevector <16 x i16> %b.not.ele, <16 x i16> poison, <16 x i32> zeroinitializer
140+
%v0.not = xor <16 x i16> %v0, splat (i16 -1)
141+
%and = and <16 x i16> %v0.not, %v1.not
142+
store <16 x i16> %and, ptr %res
143+
ret void
144+
}
145+
146+
define void @post_not_and_not_combine_v16i16(ptr %res, ptr %a, i16 %b) nounwind {
147+
; CHECK-LABEL: post_not_and_not_combine_v16i16:
148+
; CHECK: # %bb.0:
149+
; CHECK-NEXT: xvld $xr0, $a1, 0
150+
; CHECK-NEXT: xvreplgr2vr.h $xr1, $a2
151+
; CHECK-NEXT: xvrepli.b $xr2, -1
152+
; CHECK-NEXT: xvxor.v $xr1, $xr1, $xr2
153+
; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr1
154+
; CHECK-NEXT: xvst $xr0, $a0, 0
155+
; CHECK-NEXT: ret
156+
%v0 = load <16 x i16>, ptr %a
157+
%b.ele = insertelement <16 x i16> poison, i16 %b, i64 0
158+
%v1 = shufflevector <16 x i16> %b.ele, <16 x i16> poison, <16 x i32> zeroinitializer
159+
%v0.not = xor <16 x i16> %v0, splat (i16 -1)
160+
%v1.not = xor <16 x i16> %v1, splat (i16 -1)
161+
%and = and <16 x i16> %v0.not, %v1.not
162+
store <16 x i16> %and, ptr %res
163+
ret void
164+
}
165+
166+
define void @pre_not_and_not_combine_v8i32(ptr %res, ptr %a, i32 %b) nounwind {
167+
; CHECK-LABEL: pre_not_and_not_combine_v8i32:
168+
; CHECK: # %bb.0:
169+
; CHECK-NEXT: xvld $xr0, $a1, 0
170+
; CHECK-NEXT: nor $a1, $a2, $zero
171+
; CHECK-NEXT: xvreplgr2vr.w $xr1, $a1
172+
; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr1
173+
; CHECK-NEXT: xvst $xr0, $a0, 0
174+
; CHECK-NEXT: ret
175+
%v0 = load <8 x i32>, ptr %a
176+
%b.not = xor i32 %b, -1
177+
%b.not.ele = insertelement <8 x i32> poison, i32 %b.not, i64 0
178+
%v1.not = shufflevector <8 x i32> %b.not.ele, <8 x i32> poison, <8 x i32> zeroinitializer
179+
%v0.not = xor <8 x i32> %v0, splat (i32 -1)
180+
%and = and <8 x i32> %v0.not, %v1.not
181+
store <8 x i32> %and, ptr %res
182+
ret void
183+
}
184+
185+
define void @post_not_and_not_combine_v8i32(ptr %res, ptr %a, i32 %b) nounwind {
186+
; CHECK-LABEL: post_not_and_not_combine_v8i32:
187+
; CHECK: # %bb.0:
188+
; CHECK-NEXT: xvld $xr0, $a1, 0
189+
; CHECK-NEXT: xvreplgr2vr.w $xr1, $a2
190+
; CHECK-NEXT: xvrepli.b $xr2, -1
191+
; CHECK-NEXT: xvxor.v $xr1, $xr1, $xr2
192+
; CHECK-NEXT: xvandn.v $xr0, $xr0, $xr1
193+
; CHECK-NEXT: xvst $xr0, $a0, 0
194+
; CHECK-NEXT: ret
195+
%v0 = load <8 x i32>, ptr %a
196+
%b.ele = insertelement <8 x i32> poison, i32 %b, i64 0
197+
%v1 = shufflevector <8 x i32> %b.ele, <8 x i32> poison, <8 x i32> zeroinitializer
198+
%v0.not = xor <8 x i32> %v0, splat (i32 -1)
199+
%v1.not = xor <8 x i32> %v1, splat (i32 -1)
200+
%and = and <8 x i32> %v0.not, %v1.not
201+
store <8 x i32> %and, ptr %res
202+
ret void
203+
}
204+
205+
define void @pre_not_and_not_combine_v4i64(ptr %res, ptr %a, i64 %b) nounwind {
206+
; LA32-LABEL: pre_not_and_not_combine_v4i64:
207+
; LA32: # %bb.0:
208+
; LA32-NEXT: xvld $xr0, $a1, 0
209+
; LA32-NEXT: nor $a1, $a3, $zero
210+
; LA32-NEXT: nor $a2, $a2, $zero
211+
; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 0
212+
; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 1
213+
; LA32-NEXT: xvreplve0.d $xr1, $xr1
214+
; LA32-NEXT: xvandn.v $xr0, $xr0, $xr1
215+
; LA32-NEXT: xvst $xr0, $a0, 0
216+
; LA32-NEXT: ret
217+
;
218+
; LA64-LABEL: pre_not_and_not_combine_v4i64:
219+
; LA64: # %bb.0:
220+
; LA64-NEXT: xvld $xr0, $a1, 0
221+
; LA64-NEXT: nor $a1, $a2, $zero
222+
; LA64-NEXT: xvreplgr2vr.d $xr1, $a1
223+
; LA64-NEXT: xvandn.v $xr0, $xr0, $xr1
224+
; LA64-NEXT: xvst $xr0, $a0, 0
225+
; LA64-NEXT: ret
226+
%v0 = load <4 x i64>, ptr %a
227+
%b.not = xor i64 %b, -1
228+
%b.not.ele = insertelement <4 x i64> poison, i64 %b.not, i64 0
229+
%v1.not = shufflevector <4 x i64> %b.not.ele, <4 x i64> poison, <4 x i32> zeroinitializer
230+
%v0.not = xor <4 x i64> %v0, splat (i64 -1)
231+
%and = and <4 x i64> %v0.not, %v1.not
232+
store <4 x i64> %and, ptr %res
233+
ret void
234+
}
235+
236+
define void @post_not_and_not_combine_v4i64(ptr %res, ptr %a, i64 %b) nounwind {
237+
; LA32-LABEL: post_not_and_not_combine_v4i64:
238+
; LA32: # %bb.0:
239+
; LA32-NEXT: xvld $xr0, $a1, 0
240+
; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 0
241+
; LA32-NEXT: vinsgr2vr.w $vr1, $a3, 1
242+
; LA32-NEXT: xvreplve0.d $xr1, $xr1
243+
; LA32-NEXT: xvrepli.b $xr2, -1
244+
; LA32-NEXT: xvxor.v $xr1, $xr1, $xr2
245+
; LA32-NEXT: xvandn.v $xr0, $xr0, $xr1
246+
; LA32-NEXT: xvst $xr0, $a0, 0
247+
; LA32-NEXT: ret
248+
;
249+
; LA64-LABEL: post_not_and_not_combine_v4i64:
250+
; LA64: # %bb.0:
251+
; LA64-NEXT: xvld $xr0, $a1, 0
252+
; LA64-NEXT: xvreplgr2vr.d $xr1, $a2
253+
; LA64-NEXT: xvrepli.b $xr2, -1
254+
; LA64-NEXT: xvxor.v $xr1, $xr1, $xr2
255+
; LA64-NEXT: xvandn.v $xr0, $xr0, $xr1
256+
; LA64-NEXT: xvst $xr0, $a0, 0
257+
; LA64-NEXT: ret
258+
%v0 = load <4 x i64>, ptr %a
259+
%b.ele = insertelement <4 x i64> poison, i64 %b, i64 0
260+
%v1 = shufflevector <4 x i64> %b.ele, <4 x i64> poison, <4 x i32> zeroinitializer
261+
%v0.not = xor <4 x i64> %v0, splat (i64 -1)
262+
%v1.not = xor <4 x i64> %v1, splat (i64 -1)
263+
%and = and <4 x i64> %v0.not, %v1.not
264+
store <4 x i64> %and, ptr %res
265+
ret void
266+
}

‎llvm/test/CodeGen/LoongArch/lsx/and-not-combine.ll‎

Lines changed: 181 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2-
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
3-
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
2+
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
3+
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
44

55
define void @and_not_combine_v16i8(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
66
; CHECK-LABEL: and_not_combine_v16i8:
@@ -85,3 +85,182 @@ entry:
8585
store <2 x i64> %and, ptr %res
8686
ret void
8787
}
88+
89+
define void @pre_not_and_not_combine_v16i8(ptr %res, ptr %a, i8 %b) nounwind {
90+
; CHECK-LABEL: pre_not_and_not_combine_v16i8:
91+
; CHECK: # %bb.0:
92+
; CHECK-NEXT: vld $vr0, $a1, 0
93+
; CHECK-NEXT: nor $a1, $a2, $zero
94+
; CHECK-NEXT: vreplgr2vr.b $vr1, $a1
95+
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
96+
; CHECK-NEXT: vst $vr0, $a0, 0
97+
; CHECK-NEXT: ret
98+
%v0 = load <16 x i8>, ptr %a
99+
%b.not = xor i8 %b, -1
100+
%b.not.ele = insertelement <16 x i8> poison, i8 %b.not, i64 0
101+
%v1.not = shufflevector <16 x i8> %b.not.ele, <16 x i8> poison, <16 x i32> zeroinitializer
102+
%v0.not = xor <16 x i8> %v0, splat (i8 -1)
103+
%and = and <16 x i8> %v0.not, %v1.not
104+
store <16 x i8> %and, ptr %res
105+
ret void
106+
}
107+
108+
define void @post_not_and_not_combine_v16i8(ptr %res, ptr %a, i8 %b) nounwind {
109+
; CHECK-LABEL: post_not_and_not_combine_v16i8:
110+
; CHECK: # %bb.0:
111+
; CHECK-NEXT: vld $vr0, $a1, 0
112+
; CHECK-NEXT: vreplgr2vr.b $vr1, $a2
113+
; CHECK-NEXT: vxori.b $vr1, $vr1, 255
114+
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
115+
; CHECK-NEXT: vst $vr0, $a0, 0
116+
; CHECK-NEXT: ret
117+
%v0 = load <16 x i8>, ptr %a
118+
%b.ele = insertelement <16 x i8> poison, i8 %b, i64 0
119+
%v1 = shufflevector <16 x i8> %b.ele, <16 x i8> poison, <16 x i32> zeroinitializer
120+
%v0.not = xor <16 x i8> %v0, splat (i8 -1)
121+
%v1.not = xor <16 x i8> %v1, splat (i8 -1)
122+
%and = and <16 x i8> %v0.not, %v1.not
123+
store <16 x i8> %and, ptr %res
124+
ret void
125+
}
126+
127+
define void @pre_not_and_not_combine_v8i16(ptr %res, ptr %a, i16 %b) nounwind {
128+
; CHECK-LABEL: pre_not_and_not_combine_v8i16:
129+
; CHECK: # %bb.0:
130+
; CHECK-NEXT: vld $vr0, $a1, 0
131+
; CHECK-NEXT: nor $a1, $a2, $zero
132+
; CHECK-NEXT: vreplgr2vr.h $vr1, $a1
133+
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
134+
; CHECK-NEXT: vst $vr0, $a0, 0
135+
; CHECK-NEXT: ret
136+
%v0 = load <8 x i16>, ptr %a
137+
%b.not = xor i16 %b, -1
138+
%b.not.ele = insertelement <8 x i16> poison, i16 %b.not, i64 0
139+
%v1.not = shufflevector <8 x i16> %b.not.ele, <8 x i16> poison, <8 x i32> zeroinitializer
140+
%v0.not = xor <8 x i16> %v0, splat (i16 -1)
141+
%and = and <8 x i16> %v0.not, %v1.not
142+
store <8 x i16> %and, ptr %res
143+
ret void
144+
}
145+
146+
define void @post_not_and_not_combine_v8i16(ptr %res, ptr %a, i16 %b) nounwind {
147+
; CHECK-LABEL: post_not_and_not_combine_v8i16:
148+
; CHECK: # %bb.0:
149+
; CHECK-NEXT: vld $vr0, $a1, 0
150+
; CHECK-NEXT: vreplgr2vr.h $vr1, $a2
151+
; CHECK-NEXT: vrepli.b $vr2, -1
152+
; CHECK-NEXT: vxor.v $vr1, $vr1, $vr2
153+
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
154+
; CHECK-NEXT: vst $vr0, $a0, 0
155+
; CHECK-NEXT: ret
156+
%v0 = load <8 x i16>, ptr %a
157+
%b.ele = insertelement <8 x i16> poison, i16 %b, i64 0
158+
%v1 = shufflevector <8 x i16> %b.ele, <8 x i16> poison, <8 x i32> zeroinitializer
159+
%v0.not = xor <8 x i16> %v0, splat (i16 -1)
160+
%v1.not = xor <8 x i16> %v1, splat (i16 -1)
161+
%and = and <8 x i16> %v0.not, %v1.not
162+
store <8 x i16> %and, ptr %res
163+
ret void
164+
}
165+
166+
define void @pre_not_and_not_combine_v4i32(ptr %res, ptr %a, i32 %b) nounwind {
167+
; CHECK-LABEL: pre_not_and_not_combine_v4i32:
168+
; CHECK: # %bb.0:
169+
; CHECK-NEXT: vld $vr0, $a1, 0
170+
; CHECK-NEXT: nor $a1, $a2, $zero
171+
; CHECK-NEXT: vreplgr2vr.w $vr1, $a1
172+
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
173+
; CHECK-NEXT: vst $vr0, $a0, 0
174+
; CHECK-NEXT: ret
175+
%v0 = load <4 x i32>, ptr %a
176+
%b.not = xor i32 %b, -1
177+
%b.not.ele = insertelement <4 x i32> poison, i32 %b.not, i64 0
178+
%v1.not = shufflevector <4 x i32> %b.not.ele, <4 x i32> poison, <4 x i32> zeroinitializer
179+
%v0.not = xor <4 x i32> %v0, splat (i32 -1)
180+
%and = and <4 x i32> %v0.not, %v1.not
181+
store <4 x i32> %and, ptr %res
182+
ret void
183+
}
184+
185+
define void @post_not_and_not_combine_v4i32(ptr %res, ptr %a, i32 %b) nounwind {
186+
; CHECK-LABEL: post_not_and_not_combine_v4i32:
187+
; CHECK: # %bb.0:
188+
; CHECK-NEXT: vld $vr0, $a1, 0
189+
; CHECK-NEXT: vreplgr2vr.w $vr1, $a2
190+
; CHECK-NEXT: vrepli.b $vr2, -1
191+
; CHECK-NEXT: vxor.v $vr1, $vr1, $vr2
192+
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
193+
; CHECK-NEXT: vst $vr0, $a0, 0
194+
; CHECK-NEXT: ret
195+
%v0 = load <4 x i32>, ptr %a
196+
%b.ele = insertelement <4 x i32> poison, i32 %b, i64 0
197+
%v1 = shufflevector <4 x i32> %b.ele, <4 x i32> poison, <4 x i32> zeroinitializer
198+
%v0.not = xor <4 x i32> %v0, splat (i32 -1)
199+
%v1.not = xor <4 x i32> %v1, splat (i32 -1)
200+
%and = and <4 x i32> %v0.not, %v1.not
201+
store <4 x i32> %and, ptr %res
202+
ret void
203+
}
204+
205+
define void @pre_not_and_not_combine_v2i64(ptr %res, ptr %a, i64 %b) nounwind {
206+
; LA32-LABEL: pre_not_and_not_combine_v2i64:
207+
; LA32: # %bb.0:
208+
; LA32-NEXT: vld $vr0, $a1, 0
209+
; LA32-NEXT: nor $a1, $a3, $zero
210+
; LA32-NEXT: nor $a2, $a2, $zero
211+
; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 0
212+
; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 1
213+
; LA32-NEXT: vreplvei.d $vr1, $vr1, 0
214+
; LA32-NEXT: vandn.v $vr0, $vr0, $vr1
215+
; LA32-NEXT: vst $vr0, $a0, 0
216+
; LA32-NEXT: ret
217+
;
218+
; LA64-LABEL: pre_not_and_not_combine_v2i64:
219+
; LA64: # %bb.0:
220+
; LA64-NEXT: vld $vr0, $a1, 0
221+
; LA64-NEXT: nor $a1, $a2, $zero
222+
; LA64-NEXT: vreplgr2vr.d $vr1, $a1
223+
; LA64-NEXT: vandn.v $vr0, $vr0, $vr1
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; LA64-NEXT: vst $vr0, $a0, 0
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; LA64-NEXT: ret
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%v0 = load <2 x i64>, ptr %a
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%b.not = xor i64 %b, -1
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%b.not.ele = insertelement <2 x i64> poison, i64 %b.not, i64 0
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%v1.not = shufflevector <2 x i64> %b.not.ele, <2 x i64> poison, <2 x i32> zeroinitializer
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%v0.not = xor <2 x i64> %v0, splat (i64 -1)
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%and = and <2 x i64> %v0.not, %v1.not
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store <2 x i64> %and, ptr %res
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ret void
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}
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define void @post_not_and_not_combine_v2i64(ptr %res, ptr %a, i64 %b) nounwind {
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; LA32-LABEL: post_not_and_not_combine_v2i64:
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; LA32: # %bb.0:
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; LA32-NEXT: vld $vr0, $a1, 0
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; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 0
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; LA32-NEXT: vinsgr2vr.w $vr1, $a3, 1
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; LA32-NEXT: vreplvei.d $vr1, $vr1, 0
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; LA32-NEXT: vrepli.b $vr2, -1
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; LA32-NEXT: vxor.v $vr1, $vr1, $vr2
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; LA32-NEXT: vandn.v $vr0, $vr0, $vr1
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; LA32-NEXT: vst $vr0, $a0, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: post_not_and_not_combine_v2i64:
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; LA64: # %bb.0:
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; LA64-NEXT: vld $vr0, $a1, 0
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; LA64-NEXT: vreplgr2vr.d $vr1, $a2
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; LA64-NEXT: vrepli.b $vr2, -1
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; LA64-NEXT: vxor.v $vr1, $vr1, $vr2
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; LA64-NEXT: vandn.v $vr0, $vr0, $vr1
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; LA64-NEXT: vst $vr0, $a0, 0
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; LA64-NEXT: ret
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%v0 = load <2 x i64>, ptr %a
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%b.ele = insertelement <2 x i64> poison, i64 %b, i64 0
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%v1 = shufflevector <2 x i64> %b.ele, <2 x i64> poison, <2 x i32> zeroinitializer
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%v0.not = xor <2 x i64> %v0, splat (i64 -1)
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%v1.not = xor <2 x i64> %v1, splat (i64 -1)
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%and = and <2 x i64> %v0.not, %v1.not
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store <2 x i64> %and, ptr %res
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ret void
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}

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