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[RISCV] Preserve MMO when expanding PseudoRV32ZdinxSD/PseudoRV32ZdinxLD. (#85877)
This allows the asm printer to print the stack spill/reload messages.
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2 files changed

+44
-23
lines changed

2 files changed

+44
-23
lines changed

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp‎

Lines changed: 28 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -312,10 +312,19 @@ bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
312312
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
313313
Register Hi =
314314
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
315+
316+
assert(MBBI->hasOneMemOperand() && "Expected mem operand");
317+
MachineMemOperand *OldMMO = MBBI->memoperands().front();
318+
MachineFunction *MF = MBB.getParent();
319+
MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 4);
320+
MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 4, 4);
321+
315322
BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
316323
.addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
317324
.addReg(MBBI->getOperand(1).getReg())
318-
.add(MBBI->getOperand(2));
325+
.add(MBBI->getOperand(2))
326+
.setMemRefs(MMOLo);
327+
319328
if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
320329
// FIXME: Zdinx RV32 can not work on unaligned memory.
321330
assert(!STI->hasFastUnalignedAccess());
@@ -325,13 +334,15 @@ bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
325334
BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
326335
.addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
327336
.add(MBBI->getOperand(1))
328-
.add(MBBI->getOperand(2));
337+
.add(MBBI->getOperand(2))
338+
.setMemRefs(MMOHi);
329339
} else {
330340
assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
331341
BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
332342
.addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
333343
.add(MBBI->getOperand(1))
334-
.addImm(MBBI->getOperand(2).getImm() + 4);
344+
.addImm(MBBI->getOperand(2).getImm() + 4)
345+
.setMemRefs(MMOHi);
335346
}
336347
MBBI->eraseFromParent();
337348
return true;
@@ -349,14 +360,21 @@ bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
349360
Register Hi =
350361
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
351362

363+
assert(MBBI->hasOneMemOperand() && "Expected mem operand");
364+
MachineMemOperand *OldMMO = MBBI->memoperands().front();
365+
MachineFunction *MF = MBB.getParent();
366+
MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 4);
367+
MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 4, 4);
368+
352369
// If the register of operand 1 is equal to the Lo register, then swap the
353370
// order of loading the Lo and Hi statements.
354371
bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
355372
// Order: Lo, Hi
356373
if (!IsOp1EqualToLo) {
357374
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
358375
.addReg(MBBI->getOperand(1).getReg())
359-
.add(MBBI->getOperand(2));
376+
.add(MBBI->getOperand(2))
377+
.setMemRefs(MMOLo);
360378
}
361379

362380
if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
@@ -365,20 +383,23 @@ bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
365383
MBBI->getOperand(2).setOffset(Offset + 4);
366384
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
367385
.addReg(MBBI->getOperand(1).getReg())
368-
.add(MBBI->getOperand(2));
386+
.add(MBBI->getOperand(2))
387+
.setMemRefs(MMOHi);
369388
MBBI->getOperand(2).setOffset(Offset);
370389
} else {
371390
assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
372391
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
373392
.addReg(MBBI->getOperand(1).getReg())
374-
.addImm(MBBI->getOperand(2).getImm() + 4);
393+
.addImm(MBBI->getOperand(2).getImm() + 4)
394+
.setMemRefs(MMOHi);
375395
}
376396

377397
// Order: Hi, Lo
378398
if (IsOp1EqualToLo) {
379399
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
380400
.addReg(MBBI->getOperand(1).getReg())
381-
.add(MBBI->getOperand(2));
401+
.add(MBBI->getOperand(2))
402+
.setMemRefs(MMOLo);
382403
}
383404

384405
MBBI->eraseFromParent();

‎llvm/test/CodeGen/RISCV/zdinx-large-spill.mir‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -14,28 +14,28 @@
1414
; CHECK-NEXT: .cfi_def_cfa_offset 2064
1515
; CHECK-NEXT: lui t0, 1
1616
; CHECK-NEXT: add t0, sp, t0
17-
; CHECK-NEXT: sw a0, -2040(t0)
18-
; CHECK-NEXT: sw a1, -2036(t0)
17+
; CHECK-NEXT: sw a0, -2040(t0) # 4-byte Folded Spill
18+
; CHECK-NEXT: sw a1, -2036(t0) # 4-byte Folded Spill
1919
; CHECK-NEXT: lui a0, 1
2020
; CHECK-NEXT: add a0, sp, a0
21-
; CHECK-NEXT: sw a2, -2048(a0)
22-
; CHECK-NEXT: sw a3, -2044(a0)
23-
; CHECK-NEXT: sw a4, 2040(sp)
24-
; CHECK-NEXT: sw a5, 2044(sp)
25-
; CHECK-NEXT: sw a6, 2032(sp)
26-
; CHECK-NEXT: sw a7, 2036(sp)
21+
; CHECK-NEXT: sw a2, -2048(a0) # 4-byte Folded Spill
22+
; CHECK-NEXT: sw a3, -2044(a0) # 4-byte Folded Spill
23+
; CHECK-NEXT: sw a4, 2040(sp) # 4-byte Folded Spill
24+
; CHECK-NEXT: sw a5, 2044(sp) # 4-byte Folded Spill
25+
; CHECK-NEXT: sw a6, 2032(sp) # 4-byte Folded Spill
26+
; CHECK-NEXT: sw a7, 2036(sp) # 4-byte Folded Spill
2727
; CHECK-NEXT: lui a0, 1
2828
; CHECK-NEXT: add a0, sp, a0
29-
; CHECK-NEXT: lw a1, -2036(a0)
30-
; CHECK-NEXT: lw a0, -2040(a0)
29+
; CHECK-NEXT: lw a1, -2036(a0) # 4-byte Folded Reload
30+
; CHECK-NEXT: lw a0, -2040(a0) # 4-byte Folded Reload
3131
; CHECK-NEXT: lui a0, 1
3232
; CHECK-NEXT: add a0, sp, a0
33-
; CHECK-NEXT: lw a2, -2048(a0)
34-
; CHECK-NEXT: lw a3, -2044(a0)
35-
; CHECK-NEXT: lw a4, 2040(sp)
36-
; CHECK-NEXT: lw a5, 2044(sp)
37-
; CHECK-NEXT: lw a6, 2032(sp)
38-
; CHECK-NEXT: lw a7, 2036(sp)
33+
; CHECK-NEXT: lw a2, -2048(a0) # 4-byte Folded Reload
34+
; CHECK-NEXT: lw a3, -2044(a0) # 4-byte Folded Reload
35+
; CHECK-NEXT: lw a4, 2040(sp) # 4-byte Folded Reload
36+
; CHECK-NEXT: lw a5, 2044(sp) # 4-byte Folded Reload
37+
; CHECK-NEXT: lw a6, 2032(sp) # 4-byte Folded Reload
38+
; CHECK-NEXT: lw a7, 2036(sp) # 4-byte Folded Reload
3939
; CHECK-NEXT: addi sp, sp, 2032
4040
; CHECK-NEXT: addi sp, sp, 32
4141
; CHECK-NEXT: ret

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