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Change the order of rs1 and rs1 in ins rather than in argstr
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llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -125,19 +125,25 @@ class NDSRVInstBFO<bits<3> funct3, string opcodestr>
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let mayStore = 0;
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}
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128-
class NDSRVInstRR<bits<7> funct7, string opcodestr,
129-
string argstr = "$rd, $rs1, $rs2">
128+
class NDSRVInstRR<bits<7> funct7, string opcodestr>
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: RVInstR<funct7, 0b000, OPC_CUSTOM_2,
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(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
132-
opcodestr, argstr>,
131+
opcodestr, "$rd, $rs1, $rs2">,
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Sched<[WriteIALU, ReadIALU, ReadIALU]> {
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let hasSideEffects = 0;
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let mayLoad = 0;
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let mayStore = 0;
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}
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class NDSRVInstLEA<bits<7> funct7, string opcodestr>
140-
: NDSRVInstRR<funct7, opcodestr, "$rd, $rs2, $rs1">;
139+
: RVInstR<funct7, 0b000, OPC_CUSTOM_2,
140+
(outs GPR:$rd), (ins GPR:$rs2, GPR:$rs1),
141+
opcodestr, "$rd, $rs1, $rs2">,
142+
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
143+
let hasSideEffects = 0;
144+
let mayLoad = 0;
145+
let mayStore = 0;
146+
}
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// GP: ADDI, LB, LBU
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class NDSRVInstLBGP<bits<2> funct2, string opcodestr>

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