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[X86][NFC] Change check from MIR to assemble for non EGPR instructions
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4 files changed

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‎llvm/test/CodeGen/X86/apx/no-rex2-general.ll‎

Lines changed: 73 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -1,76 +1,90 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc < %s -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+sse2,+ssse3,+egpr | FileCheck %s --check-prefix=SSE
3-
; RUN: llc < %s -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+sse2,+ssse3,+egpr,+avx | FileCheck %s --check-prefix=AVX
4-
; RUN: llc < %s -enable-new-pm -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+sse2,+ssse3,+egpr | FileCheck %s --check-prefix=SSE
5-
; RUN: llc < %s -enable-new-pm -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+sse2,+ssse3,+egpr,+avx | FileCheck %s --check-prefix=AVX
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+ssse3,+egpr | FileCheck %s --check-prefix=SSE
3+
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+ssse3,+egpr,+avx | FileCheck %s --check-prefix=AVX
64

75
define i32 @map0(ptr nocapture noundef readonly %a, i64 noundef %b) {
8-
; SSE-LABEL: name: map0
9-
; SSE: bb.0.entry:
10-
; SSE-NEXT: liveins: $rdi, $rsi
11-
; SSE-NEXT: {{ $}}
12-
; SSE-NEXT: [[COPY:%[0-9]+]]:gr64_nosp = COPY $rsi
13-
; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
14-
; SSE-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 4, [[COPY]], 0, $noreg :: (load (s32) from %ir.add.ptr)
15-
; SSE-NEXT: $eax = COPY [[MOV32rm]]
16-
; SSE-NEXT: RET 0, $eax
17-
; AVX-LABEL: name: map0
18-
; AVX: bb.0.entry:
19-
; AVX-NEXT: liveins: $rdi, $rsi
20-
; AVX-NEXT: {{ $}}
21-
; AVX-NEXT: [[COPY:%[0-9]+]]:gr64_nosp = COPY $rsi
22-
; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
23-
; AVX-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 4, [[COPY]], 0, $noreg :: (load (s32) from %ir.add.ptr)
24-
; AVX-NEXT: $eax = COPY [[MOV32rm]]
25-
; AVX-NEXT: RET 0, $eax
6+
; SSE-LABEL: map0:
7+
; SSE: # %bb.0: # %entry
8+
; SSE-NEXT: movq %rsi, %r16
9+
; SSE-NEXT: movq %rdi, %r17
10+
; SSE-NEXT: #APP
11+
; SSE-NEXT: nop
12+
; SSE-NEXT: #NO_APP
13+
; SSE-NEXT: movl (%r17,%r16,4), %eax
14+
; SSE-NEXT: retq
15+
;
16+
; AVX-LABEL: map0:
17+
; AVX: # %bb.0: # %entry
18+
; AVX-NEXT: movq %rsi, %r16
19+
; AVX-NEXT: movq %rdi, %r17
20+
; AVX-NEXT: #APP
21+
; AVX-NEXT: nop
22+
; AVX-NEXT: #NO_APP
23+
; AVX-NEXT: movl (%r17,%r16,4), %eax
24+
; AVX-NEXT: retq
2625
entry:
2726
%add.ptr = getelementptr inbounds i32, ptr %a, i64 %b
27+
tail call void asm sideeffect "nop", "~{eax},~{ecx},~{edx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
2828
%0 = load i32, ptr %add.ptr
2929
ret i32 %0
3030
}
3131

32-
define i32 @map1_or_vex(<2 x double> noundef %a) {
33-
; SSE-LABEL: name: map1_or_vex
34-
; SSE: bb.0.entry:
35-
; SSE-NEXT: liveins: $xmm0
36-
; SSE-NEXT: {{ $}}
37-
; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
38-
; SSE-NEXT: [[CVTSD2SIrr_Int:%[0-9]+]]:gr32 = nofpexcept CVTSD2SIrr_Int [[COPY]], implicit $mxcsr
39-
; SSE-NEXT: $eax = COPY [[CVTSD2SIrr_Int]]
40-
; SSE-NEXT: RET 0, $eax
41-
; AVX-LABEL: name: map1_or_vex
42-
; AVX: bb.0.entry:
43-
; AVX-NEXT: liveins: $xmm0
44-
; AVX-NEXT: {{ $}}
45-
; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
46-
; AVX-NEXT: [[VCVTSD2SIrr_Int:%[0-9]+]]:gr32_norex2 = nofpexcept VCVTSD2SIrr_Int [[COPY]], implicit $mxcsr
47-
; AVX-NEXT: $eax = COPY [[VCVTSD2SIrr_Int]]
48-
; AVX-NEXT: RET 0, $eax
32+
define i32 @map1_or_vex(<2 x double> noundef %a) nounwind {
33+
; SSE-LABEL: map1_or_vex:
34+
; SSE: # %bb.0: # %entry
35+
; SSE-NEXT: cvtsd2si %xmm0, %r16d
36+
; SSE-NEXT: #APP
37+
; SSE-NEXT: nop
38+
; SSE-NEXT: #NO_APP
39+
; SSE-NEXT: movl %r16d, %eax
40+
; SSE-NEXT: retq
41+
;
42+
; AVX-LABEL: map1_or_vex:
43+
; AVX: # %bb.0: # %entry
44+
; AVX-NEXT: pushq %rbx
45+
; AVX-NEXT: vcvtsd2si %xmm0, %ebx
46+
; AVX-NEXT: #APP
47+
; AVX-NEXT: nop
48+
; AVX-NEXT: #NO_APP
49+
; AVX-NEXT: movl %ebx, %eax
50+
; AVX-NEXT: popq %rbx
51+
; AVX-NEXT: retq
4952
entry:
5053
%0 = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %a)
54+
tail call void asm sideeffect "nop", "~{eax},~{ecx},~{edx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
5155
ret i32 %0
5256
}
5357

54-
define <2 x i64> @map2_or_vex(ptr nocapture noundef readonly %b, i64 noundef %c) {
55-
; SSE-LABEL: name: map2_or_vex
56-
; SSE: bb.0.entry:
57-
; SSE-NEXT: liveins: $rdi, $rsi
58-
; SSE-NEXT: {{ $}}
59-
; SSE-NEXT: [[COPY:%[0-9]+]]:gr64_norex2_nosp = COPY $rsi
60-
; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64_norex2 = COPY $rdi
61-
; SSE-NEXT: [[PABSBrm:%[0-9]+]]:vr128 = PABSBrm [[COPY1]], 4, [[COPY]], 0, $noreg :: (load (s128) from %ir.add.ptr)
62-
; SSE-NEXT: $xmm0 = COPY [[PABSBrm]]
63-
; SSE-NEXT: RET 0, $xmm0
64-
; AVX-LABEL: name: map2_or_vex
65-
; AVX: bb.0.entry:
66-
; AVX-NEXT: liveins: $rdi, $rsi
67-
; AVX-NEXT: {{ $}}
68-
; AVX-NEXT: [[COPY:%[0-9]+]]:gr64_norex2_nosp = COPY $rsi
69-
; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64_norex2 = COPY $rdi
70-
; AVX-NEXT: [[VPABSBrm:%[0-9]+]]:vr128 = VPABSBrm [[COPY1]], 4, [[COPY]], 0, $noreg :: (load (s128) from %ir.add.ptr)
71-
; AVX-NEXT: $xmm0 = COPY [[VPABSBrm]]
72-
; AVX-NEXT: RET 0, $xmm0
58+
define <2 x i64> @map2_or_vex(ptr nocapture noundef readonly %b, i64 noundef %c) nounwind {
59+
; SSE-LABEL: map2_or_vex:
60+
; SSE: # %bb.0: # %entry
61+
; SSE-NEXT: pushq %r14
62+
; SSE-NEXT: pushq %rbx
63+
; SSE-NEXT: movq %rsi, %rbx
64+
; SSE-NEXT: movq %rdi, %r14
65+
; SSE-NEXT: #APP
66+
; SSE-NEXT: nop
67+
; SSE-NEXT: #NO_APP
68+
; SSE-NEXT: pabsb (%r14,%rbx,4), %xmm0
69+
; SSE-NEXT: popq %rbx
70+
; SSE-NEXT: popq %r14
71+
; SSE-NEXT: retq
72+
;
73+
; AVX-LABEL: map2_or_vex:
74+
; AVX: # %bb.0: # %entry
75+
; AVX-NEXT: pushq %r14
76+
; AVX-NEXT: pushq %rbx
77+
; AVX-NEXT: movq %rsi, %rbx
78+
; AVX-NEXT: movq %rdi, %r14
79+
; AVX-NEXT: #APP
80+
; AVX-NEXT: nop
81+
; AVX-NEXT: #NO_APP
82+
; AVX-NEXT: vpabsb (%r14,%rbx,4), %xmm0
83+
; AVX-NEXT: popq %rbx
84+
; AVX-NEXT: popq %r14
85+
; AVX-NEXT: retq
7386
entry:
87+
tail call void asm sideeffect "nop", "~{eax},~{ecx},~{edx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
7488
%add.ptr = getelementptr inbounds i32, ptr %b, i64 %c
7589
%a = load <2 x i64>, ptr %add.ptr
7690
%0 = bitcast <2 x i64> %a to <16 x i8>

‎llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll‎

Lines changed: 16 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,20 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc < %s -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+amx-tile,+egpr | FileCheck %s
3-
; RUN: llc < %s -enable-new-pm -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+amx-tile,+egpr | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+amx-tile,+egpr | FileCheck %s
43

5-
define dso_local void @amx(ptr noundef %data) {
6-
; CHECK-LABEL: name: amx
7-
; CHECK: bb.0.entry:
8-
; CHECK-NEXT: liveins: $rdi
9-
; CHECK-NEXT: {{ $}}
10-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64_norex2 = COPY $rdi
11-
; CHECK-NEXT: [[MOV32ri64_:%[0-9]+]]:gr64_norex2_nosp = MOV32ri64 8
12-
; CHECK-NEXT: PTILELOADD 4, [[COPY]], 1, killed [[MOV32ri64_]], 0, $noreg
13-
; CHECK-NEXT: RET 0
14-
entry:
4+
define dso_local void @amx(ptr noundef %data) nounwind {
5+
; CHECK-LABEL: amx:
6+
; CHECK: # %bb.0: # %entry
7+
; CHECK-NEXT: pushq %rbx
8+
; CHECK-NEXT: movq %rdi, %rbx
9+
; CHECK-NEXT: #APP
10+
; CHECK-NEXT: nop
11+
; CHECK-NEXT: #NO_APP
12+
; CHECK-NEXT: movl $8, %eax
13+
; CHECK-NEXT: tileloadd (%rbx,%rax), %tmm4
14+
; CHECK-NEXT: popq %rbx
15+
; CHECK-NEXT: retq
16+
entry:
17+
tail call void asm sideeffect "nop", "~{eax},~{ecx},~{edx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
1518
call void @llvm.x86.tileloadd64(i8 4, ptr %data, i64 8)
1619
ret void
1720
}

‎llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll‎

Lines changed: 18 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,22 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc < %s -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=-sse,+egpr | FileCheck %s
3-
; RUN: llc < %s -enable-new-pm -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=-sse,+egpr | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=-sse,+egpr | FileCheck %s
43

5-
define void @x87(ptr %0, ptr %1) {
6-
; CHECK-LABEL: name: x87
7-
; CHECK: bb.0 (%ir-block.2):
8-
; CHECK-NEXT: liveins: $rdi, $rsi
9-
; CHECK-NEXT: {{ $}}
10-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64_norex2 = COPY $rsi
11-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64_norex2 = COPY $rdi
12-
; CHECK-NEXT: [[LD_Fp32m:%[0-9]+]]:rfp32 = nofpexcept LD_Fp32m [[COPY1]], 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %ir.0)
13-
; CHECK-NEXT: nofpexcept ST_Fp32m [[COPY]], 1, $noreg, 0, $noreg, killed [[LD_Fp32m]], implicit-def dead $fpsw, implicit $fpcw :: (store (s32) into %ir.1)
14-
; CHECK-NEXT: RET 0
4+
define void @x87(ptr %0, ptr %1) nounwind {
5+
; CHECK-LABEL: x87:
6+
; CHECK: # %bb.0:
7+
; CHECK-NEXT: pushq %r14
8+
; CHECK-NEXT: pushq %rbx
9+
; CHECK-NEXT: movq %rsi, %rbx
10+
; CHECK-NEXT: movq %rdi, %r14
11+
; CHECK-NEXT: #APP
12+
; CHECK-NEXT: nop
13+
; CHECK-NEXT: #NO_APP
14+
; CHECK-NEXT: flds (%r14)
15+
; CHECK-NEXT: fstps (%rbx)
16+
; CHECK-NEXT: popq %rbx
17+
; CHECK-NEXT: popq %r14
18+
; CHECK-NEXT: retq
19+
tail call void asm sideeffect "nop", "~{eax},~{ecx},~{edx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
1520
%3 = load float, ptr %0
1621
store float %3, ptr %1
1722
ret void

‎llvm/test/CodeGen/X86/apx/no-rex2-special.ll‎

Lines changed: 62 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -1,70 +1,81 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc < %s -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+xsave,+egpr | FileCheck %s
3-
; RUN: llc < %s -enable-new-pm -mtriple=x86_64-unknown -stop-after=x86-isel -mattr=+xsave,+egpr | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+xsave,+egpr | FileCheck %s
43

5-
define void @test_xsave(ptr %ptr, i32 %hi, i32 %lo) {
6-
; CHECK-LABEL: name: test_xsave
7-
; CHECK: bb.0 (%ir-block.0):
8-
; CHECK-NEXT: liveins: $rdi, $esi, $edx
9-
; CHECK-NEXT: {{ $}}
10-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
11-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
12-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64_norex2 = COPY $rdi
13-
; CHECK-NEXT: $edx = COPY [[COPY1]]
14-
; CHECK-NEXT: $eax = COPY [[COPY]]
15-
; CHECK-NEXT: XSAVE [[COPY2]], 1, $noreg, 0, $noreg, implicit $edx, implicit $eax
16-
; CHECK-NEXT: RET 0
4+
define void @test_xsave(ptr %ptr, i32 %hi, i32 %lo) nounwind {
5+
; CHECK-LABEL: test_xsave:
6+
; CHECK: # %bb.0:
7+
; CHECK-NEXT: pushq %rbx
8+
; CHECK-NEXT: movl %edx, %r16d
9+
; CHECK-NEXT: movl %esi, %edx
10+
; CHECK-NEXT: movq %rdi, %rbx
11+
; CHECK-NEXT: #APP
12+
; CHECK-NEXT: nop
13+
; CHECK-NEXT: #NO_APP
14+
; CHECK-NEXT: movl %r16d, %eax
15+
; CHECK-NEXT: xsave (%rbx)
16+
; CHECK-NEXT: popq %rbx
17+
; CHECK-NEXT: retq
18+
tail call void asm sideeffect "nop", "~{eax},~{ecx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
1719
call void @llvm.x86.xsave(ptr %ptr, i32 %hi, i32 %lo)
1820
ret void;
1921
}
2022
declare void @llvm.x86.xsave(ptr, i32, i32)
2123

22-
define void @test_xsave64(ptr %ptr, i32 %hi, i32 %lo) {
23-
; CHECK-LABEL: name: test_xsave64
24-
; CHECK: bb.0 (%ir-block.0):
25-
; CHECK-NEXT: liveins: $rdi, $esi, $edx
26-
; CHECK-NEXT: {{ $}}
27-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
28-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
29-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64_norex2 = COPY $rdi
30-
; CHECK-NEXT: $edx = COPY [[COPY1]]
31-
; CHECK-NEXT: $eax = COPY [[COPY]]
32-
; CHECK-NEXT: XSAVE64 [[COPY2]], 1, $noreg, 0, $noreg, implicit $edx, implicit $eax
33-
; CHECK-NEXT: RET 0
24+
define void @test_xsave64(ptr %ptr, i32 %hi, i32 %lo) nounwind {
25+
; CHECK-LABEL: test_xsave64:
26+
; CHECK: # %bb.0:
27+
; CHECK-NEXT: pushq %rbx
28+
; CHECK-NEXT: movl %edx, %r16d
29+
; CHECK-NEXT: movl %esi, %edx
30+
; CHECK-NEXT: movq %rdi, %rbx
31+
; CHECK-NEXT: #APP
32+
; CHECK-NEXT: nop
33+
; CHECK-NEXT: #NO_APP
34+
; CHECK-NEXT: movl %r16d, %eax
35+
; CHECK-NEXT: xsave64 (%rbx)
36+
; CHECK-NEXT: popq %rbx
37+
; CHECK-NEXT: retq
38+
tail call void asm sideeffect "nop", "~{eax},~{ecx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
3439
call void @llvm.x86.xsave64(ptr %ptr, i32 %hi, i32 %lo)
3540
ret void;
3641
}
3742
declare void @llvm.x86.xsave64(ptr, i32, i32)
3843

39-
define void @test_xrstor(ptr %ptr, i32 %hi, i32 %lo) {
40-
; CHECK-LABEL: name: test_xrstor
41-
; CHECK: bb.0 (%ir-block.0):
42-
; CHECK-NEXT: liveins: $rdi, $esi, $edx
43-
; CHECK-NEXT: {{ $}}
44-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
45-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
46-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64_norex2 = COPY $rdi
47-
; CHECK-NEXT: $edx = COPY [[COPY1]]
48-
; CHECK-NEXT: $eax = COPY [[COPY]]
49-
; CHECK-NEXT: XRSTOR [[COPY2]], 1, $noreg, 0, $noreg, implicit $edx, implicit $eax
50-
; CHECK-NEXT: RET 0
44+
define void @test_xrstor(ptr %ptr, i32 %hi, i32 %lo) nounwind {
45+
; CHECK-LABEL: test_xrstor:
46+
; CHECK: # %bb.0:
47+
; CHECK-NEXT: pushq %rbx
48+
; CHECK-NEXT: movl %edx, %r16d
49+
; CHECK-NEXT: movl %esi, %edx
50+
; CHECK-NEXT: movq %rdi, %rbx
51+
; CHECK-NEXT: #APP
52+
; CHECK-NEXT: nop
53+
; CHECK-NEXT: #NO_APP
54+
; CHECK-NEXT: movl %r16d, %eax
55+
; CHECK-NEXT: xrstor (%rbx)
56+
; CHECK-NEXT: popq %rbx
57+
; CHECK-NEXT: retq
58+
tail call void asm sideeffect "nop", "~{eax},~{ecx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
5159
call void @llvm.x86.xrstor(ptr %ptr, i32 %hi, i32 %lo)
5260
ret void;
5361
}
5462
declare void @llvm.x86.xrstor(ptr, i32, i32)
5563

56-
define void @test_xrstor64(ptr %ptr, i32 %hi, i32 %lo) {
57-
; CHECK-LABEL: name: test_xrstor64
58-
; CHECK: bb.0 (%ir-block.0):
59-
; CHECK-NEXT: liveins: $rdi, $esi, $edx
60-
; CHECK-NEXT: {{ $}}
61-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
62-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
63-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64_norex2 = COPY $rdi
64-
; CHECK-NEXT: $edx = COPY [[COPY1]]
65-
; CHECK-NEXT: $eax = COPY [[COPY]]
66-
; CHECK-NEXT: XRSTOR64 [[COPY2]], 1, $noreg, 0, $noreg, implicit $edx, implicit $eax
67-
; CHECK-NEXT: RET 0
64+
define void @test_xrstor64(ptr %ptr, i32 %hi, i32 %lo) nounwind {
65+
; CHECK-LABEL: test_xrstor64:
66+
; CHECK: # %bb.0:
67+
; CHECK-NEXT: pushq %rbx
68+
; CHECK-NEXT: movl %edx, %r16d
69+
; CHECK-NEXT: movl %esi, %edx
70+
; CHECK-NEXT: movq %rdi, %rbx
71+
; CHECK-NEXT: #APP
72+
; CHECK-NEXT: nop
73+
; CHECK-NEXT: #NO_APP
74+
; CHECK-NEXT: movl %r16d, %eax
75+
; CHECK-NEXT: xrstor64 (%rbx)
76+
; CHECK-NEXT: popq %rbx
77+
; CHECK-NEXT: retq
78+
tail call void asm sideeffect "nop", "~{eax},~{ecx},~{esi},~{edi},~{r8},~{r9},~{r10},~{r11}"()
6879
call void @llvm.x86.xrstor64(ptr %ptr, i32 %hi, i32 %lo)
6980
ret void;
7081
}

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