Split spills-to-memory from satisfied.

Author: jmmartinez

llvm/lib/Target/AMDGPU/GCNRegPressure.cpp

@@ -428,8 +428,16 @@ bool GCNRPTarget::isSaveBeneficial(Register Reg) const {
 }
 
 bool GCNRPTarget::satisfied() const {
+  if (RP.getSGPRNum() > MaxSGPRs || RP.getVGPRNum(false) > MaxVGPRs)
+    return false;
+  if (UnifiedRF && RP.getVGPRNum(true) > MaxUnifiedVGPRs)
+    return false;
+  return true;
+}
+
+bool GCNRPTarget::spillsToMemory() const {
   RegExcess Excess(MF, RP, MaxSGPRs, MaxVGPRs);
-  return !Excess.spillsToMemory();
+  return Excess.spillsToMemory();
 }
 
 ///////////////////////////////////////////////////////////////////////////////

llvm/lib/Target/AMDGPU/GCNRegPressure.h

@@ -234,6 +234,7 @@ class GCNRPTarget {
 
   /// Whether the current RP is at or below the defined pressure target.
   bool satisfied() const;
+  bool spillsToMemory() const;
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
   friend raw_ostream &operator<<(raw_ostream &OS, const GCNRPTarget &Target) {

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

@@ -2046,14 +2046,16 @@ bool PreRARematStage::setObjective() {
   // Set up "spilling targets" for all regions.
   unsigned MaxSGPRs = ST.getMaxNumSGPRs(F);
   unsigned MaxVGPRs = ST.getMaxNumVGPRs(F);
+  bool SpillsToMemory = false;
   for (unsigned I = 0, E = DAG.Regions.size(); I != E; ++I) {
     const GCNRegPressure &RP = DAG.Pressure[I];
     GCNRPTarget &Target = RPTargets.emplace_back(MaxSGPRs, MaxVGPRs, MF, RP);
     if (!Target.satisfied())
       TargetRegions.set(I);
+    SpillsToMemory |= Target.spillsToMemory();
   }
 
-  if (TargetRegions.any() || DAG.MinOccupancy >= MFI.getMaxWavesPerEU()) {
+  if (SpillsToMemory || DAG.MinOccupancy >= MFI.getMaxWavesPerEU()) {
     // In addition to register usage being above addressable limits, occupancy
     // below the minimum is considered like "spilling" as well.
     TargetOcc = std::nullopt;