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[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMUL (#167847)
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4 files changed

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‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -935,7 +935,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
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bool hasSALUFloat = ST->hasSALUFloatInsts();
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938-
addRulesForGOpcs({G_FADD}, Standard)
938+
addRulesForGOpcs({G_FADD, G_FMUL}, Standard)
939939
.Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16}}, !hasSALUFloat)
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.Uni(S16, {{Sgpr16}, {Sgpr16, Sgpr16}}, hasSALUFloat)
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.Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})

‎llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll‎

Lines changed: 165 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,165 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=-real-true16 -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-FAKE16 %s
3+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=+real-true16 -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-TRUE16 %s
4+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=-real-true16 -mcpu=gfx1200 -o - %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-FAKE16 %s
5+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=+real-true16 -mcpu=gfx1200 -o - %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-TRUE16 %s
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define amdgpu_ps half @fmul_s16_uniform(half inreg %a, half inreg %b) {
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; GFX11-FAKE16-LABEL: fmul_s16_uniform:
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; GFX11-FAKE16: ; %bb.0:
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; GFX11-FAKE16-NEXT: v_mul_f16_e64 v0, s0, s1
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; GFX11-FAKE16-NEXT: ; return to shader part epilog
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;
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; GFX11-TRUE16-LABEL: fmul_s16_uniform:
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; GFX11-TRUE16: ; %bb.0:
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; GFX11-TRUE16-NEXT: v_mul_f16_e64 v0.l, s0, s1
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; GFX11-TRUE16-NEXT: ; return to shader part epilog
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;
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; GFX12-LABEL: fmul_s16_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_mul_f16 s0, s0, s1
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: ; return to shader part epilog
24+
%result = fmul half %a, %b
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ret half %result
26+
}
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define amdgpu_ps half @fmul_s16_div(half %a, half %b) {
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; GFX11-FAKE16-LABEL: fmul_s16_div:
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; GFX11-FAKE16: ; %bb.0:
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; GFX11-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
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; GFX11-FAKE16-NEXT: ; return to shader part epilog
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;
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; GFX11-TRUE16-LABEL: fmul_s16_div:
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; GFX11-TRUE16: ; %bb.0:
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; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
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; GFX11-TRUE16-NEXT: ; return to shader part epilog
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;
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; GFX12-FAKE16-LABEL: fmul_s16_div:
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; GFX12-FAKE16: ; %bb.0:
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; GFX12-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1
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; GFX12-FAKE16-NEXT: ; return to shader part epilog
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;
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; GFX12-TRUE16-LABEL: fmul_s16_div:
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; GFX12-TRUE16: ; %bb.0:
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; GFX12-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
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; GFX12-TRUE16-NEXT: ; return to shader part epilog
48+
%result = fmul half %a, %b
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ret half %result
50+
}
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define amdgpu_ps float @fmul_s32_uniform(float inreg %a, float inreg %b) {
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; GFX11-LABEL: fmul_s32_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mul_f32_e64 v0, s0, s1
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; GFX11-NEXT: ; return to shader part epilog
57+
;
58+
; GFX12-LABEL: fmul_s32_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_mul_f32 s0, s0, s1
61+
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: ; return to shader part epilog
64+
%result = fmul float %a, %b
65+
ret float %result
66+
}
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68+
define amdgpu_ps float @fmul_s32_div(float %a, float %b) {
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; GCN-LABEL: fmul_s32_div:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_mul_f32_e32 v0, v0, v1
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; GCN-NEXT: ; return to shader part epilog
73+
%result = fmul float %a, %b
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ret float %result
75+
}
76+
77+
define amdgpu_ps void @fmul_s64_uniform(double inreg %a, double inreg %b, ptr addrspace(1) %ptr) {
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; GFX11-LABEL: fmul_s64_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mul_f64 v[2:3], s[0:1], s[2:3]
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; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
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; GFX11-NEXT: s_endpgm
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;
84+
; GFX12-LABEL: fmul_s64_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_mul_f64_e64 v[2:3], s[0:1], s[2:3]
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; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
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; GFX12-NEXT: s_endpgm
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%result = fmul double %a, %b
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store double %result, ptr addrspace(1) %ptr
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ret void
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}
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define amdgpu_ps void @fmul_s64_div(double %a, double %b, ptr addrspace(1) %ptr) {
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; GFX11-LABEL: fmul_s64_div:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3]
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; GFX11-NEXT: global_store_b64 v[4:5], v[0:1], off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: fmul_s64_div:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_mul_f64_e32 v[0:1], v[0:1], v[2:3]
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; GFX12-NEXT: global_store_b64 v[4:5], v[0:1], off
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; GFX12-NEXT: s_endpgm
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%result = fmul double %a, %b
107+
store double %result, ptr addrspace(1) %ptr
108+
ret void
109+
}
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111+
define amdgpu_ps <2 x half> @fmul_v2s16_uniform(<2 x half> inreg %a, <2 x half> inreg %b) {
112+
; GFX11-LABEL: fmul_v2s16_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_pk_mul_f16 v0, s0, s1
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX12-LABEL: fmul_v2s16_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_lshr_b32 s2, s0, 16
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; GFX12-NEXT: s_lshr_b32 s3, s1, 16
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; GFX12-NEXT: s_mul_f16 s0, s0, s1
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; GFX12-NEXT: s_mul_f16 s1, s2, s3
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s1
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: ; return to shader part epilog
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%result = fmul <2 x half> %a, %b
128+
ret <2 x half> %result
129+
}
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131+
define amdgpu_ps <2 x half> @fmul_v2s16_div(<2 x half> %a, <2 x half> %b) {
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; GCN-LABEL: fmul_v2s16_div:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_pk_mul_f16 v0, v0, v1
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; GCN-NEXT: ; return to shader part epilog
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%result = fmul <2 x half> %a, %b
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ret <2 x half> %result
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}
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define amdgpu_ps <2 x float> @fmul_v2s32_uniform(<2 x float> inreg %a, <2 x float> inreg %b) {
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; GFX11-LABEL: fmul_v2s32_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mul_f32_e64 v0, s0, s2
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; GFX11-NEXT: v_mul_f32_e64 v1, s1, s3
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; GFX11-NEXT: ; return to shader part epilog
146+
;
147+
; GFX12-LABEL: fmul_v2s32_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_mul_f32 s0, s0, s2
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; GFX12-NEXT: s_mul_f32 s1, s1, s3
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
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; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
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; GFX12-NEXT: ; return to shader part epilog
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%result = fmul <2 x float> %a, %b
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ret <2 x float> %result
156+
}
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define amdgpu_ps <2 x float> @fmul_v2s32_div(<2 x float> %a, <2 x float> %b) {
159+
; GCN-LABEL: fmul_v2s32_div:
160+
; GCN: ; %bb.0:
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; GCN-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
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; GCN-NEXT: ; return to shader part epilog
163+
%result = fmul <2 x float> %a, %b
164+
ret <2 x float> %result
165+
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,8 @@
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
55
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s
66

7+
; TODO: Switch test to use -new-reg-bank-select after adding G_FNEG support.
8+
79
define <2 x half> @v_fmul_v2f16(<2 x half> %a, <2 x half> %b) {
810
; GFX9-LABEL: v_fmul_v2f16:
911
; GFX9: ; %bb.0:

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3-
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
2+
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3+
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
44

55
---
66
name: fmul_ss
@@ -17,6 +17,7 @@ body: |
1717
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
1818
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
1919
; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY2]], [[COPY3]]
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; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[FMUL]]
2021
%0:_(s32) = COPY $sgpr0
2122
%1:_(s32) = COPY $sgpr1
2223
%2:_(s32) = G_FMUL %0, %1

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