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--Added support for extension SPV_INTEL_2d_block_io
--Added test files for the extension SPV_INTEL_2d_block_io
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8 files changed

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8 files changed

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‎llvm/docs/SPIRVUsage.rst‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -213,6 +213,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
213213
- Adds a bitwise instruction on three operands and a look-up table index for specifying the bitwise operation to perform.
214214
* - ``SPV_INTEL_subgroup_matrix_multiply_accumulate``
215215
- Adds an instruction to compute the matrix product of an M x K matrix with a K x N matrix and then add an M x N matrix.
216+
* - ``SPV_INTEL_2d_block_io``
217+
- Adds additional subgroup block load and store instructions to read two-dimensional blocks of data from a two-dimensional region of memory, or to write two-dimensional blocks of data to a two dimensional region of memory.
216218

217219
To enable multiple extensions, list them separated by comma. For example, to enable support for atomic operations on floating-point numbers and arbitrary precision integers, use:
218220

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp‎

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -697,7 +697,8 @@ static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call,
697697
MachineIRBuilder &MIRBuilder,
698698
SPIRVGlobalRegistry *GR) {
699699
if (Call->isSpirvOp())
700-
return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call, Register(0));
700+
return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call,
701+
Register(0));
701702

702703
Register ScopeRegister =
703704
buildConstantIntReg32(SPIRV::Scope::Device, MIRBuilder, GR);
@@ -2306,7 +2307,17 @@ static bool generateBindlessImageINTELInst(const SPIRV::IncomingCall *Call,
23062307

23072308
return buildBindlessImageINTELInst(Call, Opcode, MIRBuilder, GR);
23082309
}
2309-
2310+
static bool generateSubgroup2DBlockInst(const SPIRV::IncomingCall *Call,
2311+
MachineIRBuilder &MIRBuilder,
2312+
SPIRVGlobalRegistry *GR) {
2313+
const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
2314+
unsigned Opcode =
2315+
SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
2316+
auto MIB = MIRBuilder.buildInstr(Opcode);
2317+
for (unsigned i = 0; i < Call->Arguments.size(); i++)
2318+
MIB.addUse(Call->Arguments[i]);
2319+
return true;
2320+
}
23102321
static bool
23112322
generateTernaryBitwiseFunctionINTELInst(const SPIRV::IncomingCall *Call,
23122323
MachineIRBuilder &MIRBuilder,
@@ -2902,6 +2913,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
29022913
return generateBindlessImageINTELInst(Call.get(), MIRBuilder, GR);
29032914
case SPIRV::TernaryBitwiseINTEL:
29042915
return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
2916+
case SPIRV::Subgroup2DBlock:
2917+
return generateSubgroup2DBlockInst(Call.get(), MIRBuilder, GR);
29052918
}
29062919
return false;
29072920
}

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.td‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,7 @@ def ICarryBorrow : BuiltinGroup;
6868
def ExtendedBitOps : BuiltinGroup;
6969
def BindlessINTEL : BuiltinGroup;
7070
def TernaryBitwiseINTEL : BuiltinGroup;
71+
def Subgroup2DBlock: BuiltinGroup;
7172

7273
//===----------------------------------------------------------------------===//
7374
// Class defining a demangled builtin record. The information in the record
@@ -718,6 +719,13 @@ defm : DemangledNativeBuiltin<"__spirv_ConvertHandleToSampledImageINTEL", OpenCL
718719
// SPV_INTEL_ternary_bitwise_function builtin records:
719720
defm : DemangledNativeBuiltin<"__spirv_BitwiseFunctionINTEL", OpenCL_std, TernaryBitwiseINTEL, 4, 4, OpBitwiseFunctionINTEL>;
720721

722+
//SPV_INTEL_2d_block_io
723+
defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockLoadINTEL", OpenCL_std, Subgroup2DBlock, 10, 10, OpSubgroup2DBlockLoadINTEL>;
724+
defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockLoadTransposeINTEL", OpenCL_std, Subgroup2DBlock, 10, 10, OpSubgroup2DBlockLoadTransposeINTEL>;
725+
defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockLoadTransformINTEL", OpenCL_std, Subgroup2DBlock, 10, 10, OpSubgroup2DBlockLoadTransformINTEL>;
726+
defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockPrefetchINTEL", OpenCL_std, Subgroup2DBlock, 9, 9, OpSubgroup2DBlockPrefetchINTEL>;
727+
defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockStoreINTEL", OpenCL_std, Subgroup2DBlock, 10, 10, OpSubgroup2DBlockStoreINTEL>;
728+
721729
//===----------------------------------------------------------------------===//
722730
// Class defining a work/sub group builtin that should be translated into a
723731
// SPIR-V instruction using the defined properties.

‎llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
9797
SPIRV::Extension::Extension::
9898
SPV_INTEL_subgroup_matrix_multiply_accumulate},
9999
{"SPV_INTEL_ternary_bitwise_function",
100-
SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function}};
100+
SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function},
101+
{"SPV_INTEL_2d_block_io",
102+
SPIRV::Extension::Extension::SPV_INTEL_2d_block_io}};
101103

102104
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
103105
StringRef ArgValue,

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.td‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -936,3 +936,21 @@ def OpAliasScopeListDeclINTEL: Op<5913, (outs ID:$res), (ins variable_ops),
936936
// SPV_INTEL_ternary_bitwise_function
937937
def OpBitwiseFunctionINTEL: Op<6242, (outs ID:$res), (ins TYPE:$type, ID:$a, ID:$b, ID:$c, ID:$lut_index),
938938
"$res = OpBitwiseFunctionINTEL $type $a $b $c $lut_index">;
939+
940+
941+
//SPV_INTEL_2d_block_io
942+
def OpSubgroup2DBlockLoadINTEL: Op<6231, (outs),
943+
(ins ID:$elementSize, ID:$blockWidth, ID:$blockHeight, ID:$blockCount, ID:$srcBasePointer, ID:$memoryWidth, ID:$memoryHeight, ID:$memoryPitch, ID:$coordinate, ID:$dstPointer),
944+
"OpSubgroup2DBlockLoadINTEL $elementSize $blockWidth $blockHeight $blockCount $srcBasePointer $memoryWidth $memoryHeight $memoryPitch $coordinate $dstPointer">;
945+
def OpSubgroup2DBlockLoadTransposeINTEL: Op<6232, (outs),
946+
(ins ID:$elementSize, ID:$blockWidth, ID:$blockHeight, ID:$blockCount, ID:$srcBasePointer, ID:$memoryWidth, ID:$memoryHeight, ID:$memoryPitch, ID:$coordinate, ID:$dstPointer),
947+
"OpSubgroup2DBlockLoadTransposeINTEL $elementSize $blockWidth $blockHeight $blockCount $srcBasePointer $memoryWidth $memoryHeight $memoryPitch $coordinate $dstPointer">;
948+
def OpSubgroup2DBlockLoadTransformINTEL: Op<6233, (outs),
949+
(ins ID:$elementSize, ID:$blockWidth, ID:$blockHeight, ID:$blockCount, ID:$srcBasePointer, ID:$memoryWidth, ID:$memoryHeight, ID:$memoryPitch, ID:$coordinate, ID:$dstPointer),
950+
"OpSubgroup2DBlockLoadTransformINTEL $elementSize $blockWidth $blockHeight $blockCount $srcBasePointer $memoryWidth $memoryHeight $memoryPitch $coordinate $dstPointer">;
951+
def OpSubgroup2DBlockPrefetchINTEL: Op<6234, (outs),
952+
(ins ID:$elementSize, ID:$blockWidth, ID:$blockHeight, ID:$blockCount, ID:$srcPointer, ID:$memoryWidth, ID:$memoryHeight, ID:$memoryPitch, ID:$coordinate),
953+
"OpSubgroup2DBlockPrefetchINTEL $elementSize $blockWidth $blockHeight $blockCount $srcPointer $memoryWidth $memoryHeight $memoryPitch $coordinate">;
954+
def OpSubgroup2DBlockStoreINTEL: Op<6235, (outs),
955+
(ins ID:$elementSize, ID:$blockWidth, ID:$blockHeight, ID:$blockCount, ID:$srcPointer, ID:$dstBasePointer, ID:$memoryWidth, ID:$memoryHeight, ID:$memoryPitch, ID:$coordinate),
956+
"OpSubgroup2DBlockStoreINTEL $elementSize $blockWidth $blockHeight $blockCount $srcPointer $dstBasePointer $memoryWidth $memoryHeight $memoryPitch $coordinate">;

‎llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1544,6 +1544,38 @@ void addInstrRequirements(const MachineInstr &MI,
15441544
Reqs.addCapability(SPIRV::Capability::FunctionPointersINTEL);
15451545
}
15461546
break;
1547+
case SPIRV::OpSubgroup2DBlockLoadINTEL:
1548+
case SPIRV::OpSubgroup2DBlockPrefetchINTEL:
1549+
case SPIRV::OpSubgroup2DBlockStoreINTEL: {
1550+
if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_2d_block_io))
1551+
report_fatal_error(
1552+
"OpSubgroup2DBlockLoadTransposeINTEL instruction requires the "
1553+
"following SPIR-V extension: SPV_INTEL_2d_block_io",
1554+
false);
1555+
Reqs.addExtension(SPIRV::Extension::SPV_INTEL_2d_block_io);
1556+
Reqs.addCapability(SPIRV::Capability::Subgroup2DBlockIOINTEL);
1557+
break;
1558+
}
1559+
case SPIRV::OpSubgroup2DBlockLoadTransformINTEL: {
1560+
if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_2d_block_io))
1561+
report_fatal_error(
1562+
"OpSubgroup2DBlockLoadTransformINTEL instruction requires the "
1563+
"following SPIR-V extension: SPV_INTEL_2d_block_io",
1564+
false);
1565+
Reqs.addExtension(SPIRV::Extension::SPV_INTEL_2d_block_io);
1566+
Reqs.addCapability(SPIRV::Capability::Subgroup2DBlockTransformINTEL);
1567+
break;
1568+
}
1569+
case SPIRV::OpSubgroup2DBlockLoadTransposeINTEL: {
1570+
if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_2d_block_io))
1571+
report_fatal_error(
1572+
"OpSubgroup2DBlockLoadTransposeINTEL instruction requires the "
1573+
"following SPIR-V extension: SPV_INTEL_2d_block_io",
1574+
false);
1575+
Reqs.addExtension(SPIRV::Extension::SPV_INTEL_2d_block_io);
1576+
Reqs.addCapability(SPIRV::Capability::Subgroup2DBlockTransposeINTEL);
1577+
break;
1578+
}
15471579
case SPIRV::OpAtomicFAddEXT:
15481580
case SPIRV::OpAtomicFMinEXT:
15491581
case SPIRV::OpAtomicFMaxEXT:

‎llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -315,6 +315,7 @@ defm SPV_INTEL_memory_access_aliasing : ExtensionOperand<118>;
315315
defm SPV_INTEL_fp_max_error : ExtensionOperand<119>;
316316
defm SPV_INTEL_ternary_bitwise_function : ExtensionOperand<120>;
317317
defm SPV_INTEL_subgroup_matrix_multiply_accumulate : ExtensionOperand<121>;
318+
defm SPV_INTEL_2d_block_io : ExtensionOperand<122>;
318319

319320
//===----------------------------------------------------------------------===//
320321
// Multiclass used to define Capabilities enum values and at the same time
@@ -517,6 +518,9 @@ defm MemoryAccessAliasingINTEL : CapabilityOperand<5910, 0, 0, [SPV_INTEL_memory
517518
defm FPMaxErrorINTEL : CapabilityOperand<6169, 0, 0, [SPV_INTEL_fp_max_error], []>;
518519
defm TernaryBitwiseFunctionINTEL : CapabilityOperand<6241, 0, 0, [SPV_INTEL_ternary_bitwise_function], []>;
519520
defm SubgroupMatrixMultiplyAccumulateINTEL : CapabilityOperand<6236, 0, 0, [SPV_INTEL_subgroup_matrix_multiply_accumulate], []>;
521+
defm Subgroup2DBlockIOINTEL : CapabilityOperand<6228, 0, 0, [SPV_INTEL_2d_block_io], []>;
522+
defm Subgroup2DBlockTransformINTEL : CapabilityOperand<6229, 0, 0, [SPV_INTEL_2d_block_io], []>;
523+
defm Subgroup2DBlockTransposeINTEL : CapabilityOperand<6230, 0, 0, [SPV_INTEL_2d_block_io], []>;
520524

521525
//===----------------------------------------------------------------------===//
522526
// Multiclass used to define SourceLanguage enum values and at the same time

‎llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_2d_block_io/2d_block_io_generic.ll‎

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
1+
;Generated with:
2+
; source.cl:
3+
; void __spirv_Subgroup2DBlockLoadINTEL( int element_size, int block_width, int block_height, int block_count, const __global void* src_base_pointer, int memory_width, int memory_height, int memory_pitch, int2 coordinate, private void* dst_pointer);
4+
; void __spirv_Subgroup2DBlockLoadTransposeINTEL(int element_size, int block_width, int block_height, int block_count, const __global void* src_base_pointer, int memory_width, int memory_height, int memory_pitch, int2 coordinate, private void* dst_pointer);
5+
; void __spirv_Subgroup2DBlockLoadTransformINTEL(int element_size, int block_width, int block_height, int block_count, const __global void* src_base_pointer, int memory_width, int memory_height, int memory_pitch, int2 coordinate, private void* dst_pointer);
6+
; void __spirv_Subgroup2DBlockPrefetchINTEL( int element_size, int block_width, int block_height, int block_count, const __global void* src_base_pointer, int memory_width, int memory_height, int memory_pitch, int2 coordinate );
7+
; void __spirv_Subgroup2DBlockStoreINTEL( int element_size, int block_width, int block_height, int block_count, const private void* src_pointer, __global void* dst_base_pointer, int memory_width, int memory_height, int memory_pitch, int2 coordinate );
8+
;
9+
; void foo(const __global void* base_address, __global void* dst_base_pointer, int width, int height, int pitch, int2 coord, private void* dst_pointer, const private void* src_pointer) {
10+
; const int i = 42;
11+
; __spirv_Subgroup2DBlockLoadINTEL(i, i, i, i, base_address, width, height, pitch, coord, dst_pointer);
12+
; __spirv_Subgroup2DBlockLoadTransformINTEL(i, i, i, i, base_address, width, height, pitch, coord, dst_pointer);
13+
; __spirv_Subgroup2DBlockLoadTransposeINTEL(i, i, i, i, base_address, width, height, pitch, coord, dst_pointer);
14+
; __spirv_Subgroup2DBlockPrefetchINTEL(i, i, i, i, base_address, width, height, pitch, coord);
15+
; __spirv_Subgroup2DBlockStoreINTEL(i, i, i, i, src_pointer, dst_base_pointer, width, height, pitch, coord);
16+
; }
17+
; clang -cc1 -cl-std=clc++2021 -triple spir64-unknown-unknown -emit-llvm -finclude-default-header source.cl -o tmp.ll
18+
19+
20+
21+
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_2d_block_io %s -o %t.spt
22+
; RUN: FileCheck %s --input-file=%t.spt
23+
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_2d_block_io %s -o - -filetype=obj | spirv-val %}
24+
25+
; CHECK: OpCapability Subgroup2DBlockIOINTEL
26+
; CHECK: OpCapability Subgroup2DBlockTransformINTEL
27+
; CHECK: OpCapability Subgroup2DBlockTransposeINTEL
28+
; CHECK: OpExtension "SPV_INTEL_2d_block_io"
29+
; CHECK: %[[#Int8Ty:]] = OpTypeInt 8 0
30+
; CHECK: %[[#GlbPtrTy:]] = OpTypePointer CrossWorkgroup %[[#Int8Ty]]
31+
; CHECK: %[[#Int32Ty:]] = OpTypeInt 32 0
32+
; CHECK: %[[#VectorTy:]] = OpTypeVector %[[#Int32Ty]] 2
33+
; CHECK: %[[#PrvPtrTy:]] = OpTypePointer Function %[[#Int8Ty]]
34+
; CHECK: %[[#VoidTy:]] = OpTypeVoid
35+
; CHECK: %[[#Const42:]] = OpConstant %[[#Int32Ty]] 42
36+
; CHECK: %[[#BaseSrc:]] = OpFunctionParameter %[[#GlbPtrTy]]
37+
; CHECK: %[[#BaseDst:]] = OpFunctionParameter %[[#GlbPtrTy]]
38+
; CHECK: %[[#Width:]] = OpFunctionParameter %[[#Int32Ty]]
39+
; CHECK: %[[#Height:]] = OpFunctionParameter %[[#Int32Ty]]
40+
; CHECK: %[[#Pitch:]] = OpFunctionParameter %[[#Int32Ty]]
41+
; CHECK: %[[#Coord:]] = OpFunctionParameter %[[#VectorTy]]
42+
; CHECK: %[[#Dst:]] = OpFunctionParameter %[[#PrvPtrTy]]
43+
; CHECK: %[[#Src:]] = OpFunctionParameter %[[#PrvPtrTy]]
44+
; CHECK: OpSubgroup2DBlockLoadINTEL %[[#Const42]] %[[#Const42]] %[[#Const42]] %[[#Const42]] %[[#BaseSrc]] %[[#Width]] %[[#Height]] %[[#Pitch]] %[[#Coord]] %[[#Dst]]
45+
; CHECK: OpSubgroup2DBlockLoadTransformINTEL %[[#Const42]] %[[#Const42]] %[[#Const42]] %[[#Const42]] %[[#BaseSrc]] %[[#Width]] %[[#Height]] %[[#Pitch]] %[[#Coord]] %[[#Dst]]
46+
; CHECK: OpSubgroup2DBlockLoadTransposeINTEL %[[#Const42]] %[[#Const42]] %[[#Const42]] %[[#Const42]] %[[#BaseSrc]] %[[#Width]] %[[#Height]] %[[#Pitch]] %[[#Coord]] %[[#Dst]]
47+
; CHECK: OpSubgroup2DBlockPrefetchINTEL %[[#Const42]] %[[#Const42]] %[[#Const42]] %[[#Const42]] %[[#BaseSrc]] %[[#Width]] %[[#Height]] %[[#Pitch]] %[[#Coord]]
48+
; CHECK: OpSubgroup2DBlockStoreINTEL %[[#Const42]] %[[#Const42]] %[[#Const42]] %[[#Const42]] %[[#Src]] %[[#BaseDst]] %[[#Width]] %[[#Height]] %[[#Pitch]] %[[#Coord]]
49+
50+
51+
52+
define spir_func void @foo(ptr addrspace(1) %base_address, ptr addrspace(1) %dst_base_pointer, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord, ptr %dst_pointer, ptr %src_pointer) {
53+
entry:
54+
call spir_func void @_Z32__spirv_Subgroup2DBlockLoadINTELiiiiPU3AS1KviiiDv2_iPv(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %base_address, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord, ptr %dst_pointer)
55+
call spir_func void @_Z41__spirv_Subgroup2DBlockLoadTransformINTELiiiiPU3AS1KviiiDv2_iPv(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %base_address, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord, ptr %dst_pointer)
56+
call spir_func void @_Z41__spirv_Subgroup2DBlockLoadTransposeINTELiiiiPU3AS1KviiiDv2_iPv(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %base_address, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord, ptr %dst_pointer)
57+
call spir_func void @_Z36__spirv_Subgroup2DBlockPrefetchINTELiiiiPU3AS1KviiiDv2_i(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %base_address, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord)
58+
call spir_func void @_Z33__spirv_Subgroup2DBlockStoreINTELiiiiPKvPU3AS1viiiDv2_i(i32 42, i32 42, i32 42, i32 42, ptr %src_pointer, ptr addrspace(1) %dst_base_pointer, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord)
59+
ret void
60+
}
61+
62+
declare spir_func void @_Z32__spirv_Subgroup2DBlockLoadINTELiiiiPU3AS1KviiiDv2_iPv(i32, i32, i32, i32, ptr addrspace(1), i32, i32, i32, <2 x i32>, ptr)
63+
declare spir_func void @_Z41__spirv_Subgroup2DBlockLoadTransformINTELiiiiPU3AS1KviiiDv2_iPv(i32, i32, i32, i32, ptr addrspace(1), i32, i32, i32, <2 x i32>, ptr)
64+
declare spir_func void @_Z41__spirv_Subgroup2DBlockLoadTransposeINTELiiiiPU3AS1KviiiDv2_iPv(i32, i32, i32, i32, ptr addrspace(1), i32, i32, i32, <2 x i32>, ptr)
65+
declare spir_func void @_Z36__spirv_Subgroup2DBlockPrefetchINTELiiiiPU3AS1KviiiDv2_i(i32, i32, i32, i32, ptr addrspace(1), i32, i32, i32, <2 x i32>)
66+
declare spir_func void @_Z33__spirv_Subgroup2DBlockStoreINTELiiiiPKvPU3AS1viiiDv2_i(i32, i32, i32, i32, ptr, ptr addrspace(1), i32, i32, i32, <2 x i32>)
67+
68+
!opencl.spir.version = !{!0}
69+
!spirv.Source = !{!1}
70+
!llvm.ident = !{!2}
71+
72+
!0 = !{i32 1, i32 0}
73+
!1 = !{i32 4, i32 100000}
74+
!2 = !{!"clang version 17.0.0"}

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