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| 1 | +//===----------------------- RISCVRemoveBackToBackBranches.cpp ------------===// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +//===----------------------------------------------------------------------===// |
| 8 | + |
| 9 | +#include "RISCV.h" |
| 10 | +#include "RISCVInstrInfo.h" |
| 11 | +#include "RISCVSubtarget.h" |
| 12 | +#include "llvm/ADT/Statistic.h" |
| 13 | +#include "llvm/ADT/StringRef.h" |
| 14 | +#include "llvm/CodeGen/MachineBasicBlock.h" |
| 15 | +#include "llvm/CodeGen/MachineFunction.h" |
| 16 | +#include "llvm/CodeGen/MachineFunctionPass.h" |
| 17 | +#include "llvm/CodeGen/MachineInstr.h" |
| 18 | +#include "llvm/CodeGen/TargetSubtargetInfo.h" |
| 19 | +#include "llvm/Target/TargetMachine.h" |
| 20 | + |
| 21 | +using namespace llvm; |
| 22 | + |
| 23 | +#define DEBUG_TYPE "riscv-remove-back-to-back-branches" |
| 24 | + |
| 25 | +STATISTIC(NumInsertedAligments, "Number of aligments set"); |
| 26 | + |
| 27 | +namespace { |
| 28 | + |
| 29 | +// According to the MIPS specification, there shouldn't be two conditional |
| 30 | +// branches in the same 8-byte aligned region of code. |
| 31 | +constexpr unsigned NumberOfBytesOfCodeRegion = 8; |
| 32 | + |
| 33 | +class RISCVRemoveBackToBackBranches : public MachineFunctionPass { |
| 34 | +public: |
| 35 | + static char ID; |
| 36 | + |
| 37 | + RISCVRemoveBackToBackBranches() : MachineFunctionPass(ID) { |
| 38 | + initializeRISCVRemoveBackToBackBranchesPass( |
| 39 | + *PassRegistry::getPassRegistry()); |
| 40 | + } |
| 41 | + |
| 42 | + StringRef getPassName() const override { |
| 43 | + return "RISCV Remove Back To Back Branches Pass"; |
| 44 | + } |
| 45 | + |
| 46 | + bool runOnMachineFunction(MachineFunction &F) override; |
| 47 | + |
| 48 | + MachineFunctionProperties getRequiredProperties() const override { |
| 49 | + return MachineFunctionProperties().set( |
| 50 | + MachineFunctionProperties::Property::NoVRegs); |
| 51 | + } |
| 52 | + |
| 53 | +private: |
| 54 | + const RISCVSubtarget *STI; |
| 55 | + const RISCVInstrInfo *TII; |
| 56 | +}; |
| 57 | + |
| 58 | +} // end of anonymous namespace |
| 59 | + |
| 60 | +char RISCVRemoveBackToBackBranches::ID = 0; |
| 61 | + |
| 62 | +INITIALIZE_PASS(RISCVRemoveBackToBackBranches, DEBUG_TYPE, |
| 63 | + "Fix hazards by removing back to back branches", false, false) |
| 64 | + |
| 65 | +/// Returns a pass that clears pipeline hazards. |
| 66 | +FunctionPass *llvm::createRISCVRemoveBackToBackBranches() { |
| 67 | + return new RISCVRemoveBackToBackBranches(); |
| 68 | +} |
| 69 | + |
| 70 | +static bool CheckCompressedISA(MachineBasicBlock *MBB, |
| 71 | + const RISCVInstrInfo *TII) { |
| 72 | + unsigned SizeInBytes = 0; |
| 73 | + for (auto &I : *MBB) { |
| 74 | + // Skip some 0-sized meta instrucitons, such as debug ones. |
| 75 | + if (!TII->getInstSizeInBytes(I)) |
| 76 | + continue; |
| 77 | + |
| 78 | + SizeInBytes += TII->getInstSizeInBytes(I); |
| 79 | + |
| 80 | + // This means that there is something other than the conditional branch |
| 81 | + // here. |
| 82 | + if (!I.isConditionalBranch()) |
| 83 | + continue; |
| 84 | + |
| 85 | + // If it is a conditional branch, make sure it is the last one |
| 86 | + // in this MBB and the cumulative size in bytes of other instructions in the |
| 87 | + // block is <= 6 (since there potentially could be space for the two |
| 88 | + // branches in the same 8-byte aligned code region, when compressed version |
| 89 | + // of the instructions (16-bit size) is being used). |
| 90 | + if (&I == &*MBB->getLastNonDebugInstr()) { |
| 91 | + if (SizeInBytes <= 6) |
| 92 | + return true; |
| 93 | + return false; |
| 94 | + } |
| 95 | + } |
| 96 | + |
| 97 | + return false; |
| 98 | +} |
| 99 | + |
| 100 | +static bool CheckNonCompressedISA(MachineBasicBlock *MBB, |
| 101 | + const RISCVInstrInfo *TII) { |
| 102 | + for (auto &I : *MBB) { |
| 103 | + // Skip some 0-sized meta instrucitons, such as debug ones. |
| 104 | + if (!TII->getInstSizeInBytes(I)) |
| 105 | + continue; |
| 106 | + |
| 107 | + // This means that there is something other than the conditional branch |
| 108 | + // here. |
| 109 | + if (!I.isConditionalBranch()) |
| 110 | + return false; |
| 111 | + |
| 112 | + // If it is a conditional branch, make sure it is the last one |
| 113 | + // in this MBB. |
| 114 | + if (&I == &*MBB->getLastNonDebugInstr()) |
| 115 | + return true; |
| 116 | + return false; |
| 117 | + } |
| 118 | + return false; |
| 119 | +} |
| 120 | + |
| 121 | +bool RISCVRemoveBackToBackBranches::runOnMachineFunction(MachineFunction &MF) { |
| 122 | + STI = &static_cast<const RISCVSubtarget &>(MF.getSubtarget()); |
| 123 | + TII = static_cast<const RISCVInstrInfo *>(STI->getInstrInfo()); |
| 124 | + |
| 125 | + if (!STI->shouldRemoveBackToBackBranches()) { |
| 126 | + LLVM_DEBUG(llvm::dbgs() |
| 127 | + << "Ignoring RISCV Remove Back To Back Branches Pass\n"); |
| 128 | + return false; |
| 129 | + } |
| 130 | + |
| 131 | + bool Changed = false; |
| 132 | + for (auto &MBB : MF) { |
| 133 | + auto BBTerminator = MBB.getFirstTerminator(); |
| 134 | + // If it is not a conditional branch, we are not interested. |
| 135 | + if (BBTerminator == MBB.end() || |
| 136 | + &*BBTerminator != &*MBB.getLastNonDebugInstr() || |
| 137 | + !BBTerminator->isConditionalBranch()) |
| 138 | + continue; |
| 139 | + |
| 140 | + for (auto &Successor : MBB.successors()) { |
| 141 | + // Set up aligment in order to avoid hazards. No 2 conditional branches |
| 142 | + // should be in the same 8-byte aligned region of code. Similar to MIPS |
| 143 | + // forbidden slots problem. We may want to insert a NOP only, but we |
| 144 | + // need to think of Compressed ISA, so it is more safe to just set up |
| 145 | + // aligment to the successor block if it meets requirements. |
| 146 | + bool ShouldSetAligment = STI->getFeatureBits()[RISCV::FeatureStdExtC] |
| 147 | + ? CheckCompressedISA(Successor, TII) |
| 148 | + : CheckNonCompressedISA(Successor, TII); |
| 149 | + if (ShouldSetAligment) { |
| 150 | + Successor->setAlignment(Align(NumberOfBytesOfCodeRegion)); |
| 151 | + Changed = true; |
| 152 | + ++NumInsertedAligments; |
| 153 | + } |
| 154 | + } |
| 155 | + } |
| 156 | + |
| 157 | + return Changed; |
| 158 | +} |
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