Address review comments

Author: clementval

mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td

@@ -1236,24 +1236,8 @@ def NVVM_FenceProxyAcquireOp : NVVM_Op<"fence.proxy.acquire">,
   let hasVerifier = 1;
 }
 
-// Attrs describing the level of the Memory Operation
-def MemLevelCTA : I32EnumAttrCase<"CTA", 0, "cta">;
-def MemLevelGL : I32EnumAttrCase<"GL", 1, "gl">;
-def MemLevelSys : I32EnumAttrCase<"SYS", 2, "sys">;
-
-def MemLevelKind
-    : I32EnumAttr<
-          "MemLevelKind",
-          "NVVM Memory Level kind", [MemLevelCTA, MemLevelGL, MemLevelSys]> {
-  let genSpecializedAttr = 0;
-  let cppNamespace = "::mlir::NVVM";
-}
-def MemLevelKindAttr : EnumAttr<NVVM_Dialect, MemLevelKind, "mem_level"> {
-  let assemblyFormat = "`<` $value `>`";
-}
-
-def NVVM_MembarOp : NVVM_Op<"membar">,
-                    Arguments<(ins MemLevelKindAttr:$level)> {
+def NVVM_MembarOp : NVVM_Op<"memory_barrier">,
+                    Arguments<(ins MemScopeKindAttr:$scope)> {
   let summary = "Memory barrier operation";
   let description = [{
     `membar` operation guarantees that prior memory accesses requested by this
@@ -1263,9 +1247,9 @@ def NVVM_MembarOp : NVVM_Op<"membar">,
     [For more information, see PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-membar)
   }];
 
-  let assemblyFormat = "$level attr-dict";
+  let assemblyFormat = "$scope attr-dict";
   let llvmBuilder = [{
-    createIntrinsicCall(builder, getMembarLevelID($level), {});
+    createIntrinsicCall(builder, getMemoryBarrierLevelID($scope), {});
   }];
 }
 

mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp

@@ -291,15 +291,18 @@ static unsigned getUnidirectionalFenceProxyID(NVVM::ProxyKind fromProxy,
   llvm_unreachable("Unsupported proxy kinds");
 }
 
-static unsigned getMembarLevelID(NVVM::MemLevelKind level) {
-  switch (level) {
-  case NVVM::MemLevelKind::CTA: {
+static unsigned getMemoryBarrierLevelID(NVVM::MemScopeKind scope) {
+  switch (scope) {
+  case NVVM::MemScopeKind::CTA: {
     return llvm::Intrinsic::nvvm_membar_cta;
   }
-  case NVVM::MemLevelKind::GL: {
+  case NVVM::MemScopeKind::CLUSTER: {
+    return llvm::Intrinsic::nvvm_fence_sc_cluster;
+  }
+  case NVVM::MemScopeKind::GPU: {
     return llvm::Intrinsic::nvvm_membar_gl;
   }
-  case NVVM::MemLevelKind::SYS: {
+  case NVVM::MemScopeKind::SYS: {
     return llvm::Intrinsic::nvvm_membar_sys;
   }
   }

mlir/test/Target/LLVMIR/nvvm/membar.mlir

@@ -0,0 +1,14 @@
+// RUN: mlir-translate -mlir-to-llvmir %s  -split-input-file --verify-diagnostics | FileCheck %s
+
+// CHECK-lABEL: @memorybarrier()
+llvm.func @memorybarrier() {
+  // CHECK: call void @llvm.nvvm.membar.cta()
+  nvvm.memory_barrier #nvvm.mem_scope<cta>
+  // CHECK: call void @llvm.nvvm.fence.sc.cluster()
+  nvvm.memory_barrier #nvvm.mem_scope<cluster>
+  // CHECK: call void @llvm.nvvm.membar.gl()
+  nvvm.memory_barrier #nvvm.mem_scope<gpu>
+  // CHECK: call void @llvm.nvvm.membar.sys()
+  nvvm.memory_barrier #nvvm.mem_scope<sys>
+  llvm.return
+}

mlir/test/Target/LLVMIR/nvvmir.mlir

@@ -975,16 +975,3 @@ llvm.func @nanosleep() {
   nvvm.nanosleep 4000
   llvm.return
 }
-
-// -----
-
-// CHECK-lABEL: @memorybarrier()
-llvm.func @memorybarrier() {
-  // CHECK: call void @llvm.nvvm.membar.cta()
-  nvvm.membar #nvvm.mem_level<cta>
-  // CHECK: call void @llvm.nvvm.membar.gl()
-  nvvm.membar #nvvm.mem_level<gl>
-  // CHECK: call void @llvm.nvvm.membar.sys()
-  nvvm.membar #nvvm.mem_level<sys>
-  llvm.return
-}