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mariusz-sikora-at-amdkosarev
mariusz-sikora-at-amd
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kosarev
authored
[AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (#130041)
Co-authored-by: Ivan Kosarev <[email protected]>
1 parent 379a8d1 commit 4f5ccf2

14 files changed

+182
-47
lines changed

‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2824,6 +2824,17 @@ def int_amdgcn_image_bvh_dual_intersect_ray :
28242824
llvm_v3f32_ty, llvm_v2i32_ty, llvm_v4i32_ty],
28252825
[IntrReadMem, IntrWillReturn, IntrNoCallback, IntrNoFree]>;
28262826

2827+
// <vdata>, <ray_origin>, <ray_dir>
2828+
// llvm.amdgcn.image.bvh8.intersect.ray <node_ptr>, <ray_extent>,
2829+
// <instance_mask>, <ray_origin>,
2830+
// <ray_dir>, <offset>,
2831+
// <texture_descr>
2832+
def int_amdgcn_image_bvh8_intersect_ray :
2833+
Intrinsic<[llvm_v10i32_ty, llvm_v3f32_ty, llvm_v3f32_ty],
2834+
[llvm_i64_ty, llvm_float_ty, llvm_i8_ty, llvm_v3f32_ty,
2835+
llvm_v3f32_ty, llvm_i32_ty, llvm_v4i32_ty],
2836+
[IntrReadMem, IntrWillReturn, IntrNoCallback, IntrNoFree]>;
2837+
28272838
// llvm.amdgcn.permlane16.var <old> <src0> <src1> <fi> <bound_control>
28282839
def int_amdgcn_permlane16_var : ClangBuiltin<"__builtin_amdgcn_permlane16_var">,
28292840
Intrinsic<[llvm_i32_ty],

‎llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1094,10 +1094,10 @@ def FeaturePrngInst : SubtargetFeature<"prng-inst",
10941094
"Has v_prng_b32 instruction"
10951095
>;
10961096

1097-
def FeatureBVHDualInst : SubtargetFeature<"bvh-dual-inst",
1098-
"HasBVHDualInst",
1097+
def FeatureBVHDualAndBVH8Insts : SubtargetFeature<"bvh-dual-bvh-8-insts",
1098+
"HasBVHDualAndBVH8Insts",
10991099
"true",
1100-
"Has image_bvh_dual_intersect_ray instruction"
1100+
"Has image_bvh_dual_intersect_ray and image_bvh8_intersect_ray instructions"
11011101
>;
11021102

11031103
//===------------------------------------------------------------===//
@@ -1857,7 +1857,7 @@ def FeatureISAVersion12 : FeatureSet<
18571857
FeatureMaxHardClauseLength32,
18581858
Feature1_5xVGPRs,
18591859
FeatureMemoryAtomicFAddF32DenormalSupport,
1860-
FeatureBVHDualInst
1860+
FeatureBVHDualAndBVH8Insts
18611861
]>;
18621862

18631863
def FeatureISAVersion12_Generic: FeatureSet<
@@ -2513,8 +2513,8 @@ def HasBitOp3Insts : Predicate<"Subtarget->hasBitOp3Insts()">,
25132513
def HasPrngInst : Predicate<"Subtarget->hasPrngInst()">,
25142514
AssemblerPredicate<(all_of FeaturePrngInst)>;
25152515

2516-
def HasBVHDualInst : Predicate<"Subtarget->hasBVHDualInst()">,
2517-
AssemblerPredicate<(all_of FeatureBVHDualInst)>;
2516+
def HasBVHDualAndBVH8Insts : Predicate<"Subtarget->hasBVHDualAndBVH8Insts()">,
2517+
AssemblerPredicate<(all_of FeatureBVHDualAndBVH8Insts)>;
25182518

25192519
def HasFP8ConversionScaleInsts : Predicate<"Subtarget->hasFP8ConversionScaleInsts()">,
25202520
AssemblerPredicate<(all_of FeatureFP8ConversionScaleInsts)>;

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4118,6 +4118,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
41184118
}
41194119
case AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY:
41204120
case AMDGPU::G_AMDGPU_BVH_INTERSECT_RAY:
4121+
case AMDGPU::G_AMDGPU_BVH8_INTERSECT_RAY:
41214122
return selectBVHIntersectRayIntrinsic(I);
41224123
case AMDGPU::G_SBFX:
41234124
case AMDGPU::G_UBFX:

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 14 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -7198,8 +7198,8 @@ bool AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic(
71987198
return true;
71997199
}
72007200

7201-
bool AMDGPULegalizerInfo::legalizeBVHDualIntrinsic(MachineInstr &MI,
7202-
MachineIRBuilder &B) const {
7201+
bool AMDGPULegalizerInfo::legalizeBVHDualOrBVH8IntersectRayIntrinsic(
7202+
MachineInstr &MI, MachineIRBuilder &B) const {
72037203
const LLT S32 = LLT::scalar(32);
72047204
const LLT V2S32 = LLT::fixed_vector(2, 32);
72057205

@@ -7214,25 +7214,29 @@ bool AMDGPULegalizerInfo::legalizeBVHDualIntrinsic(MachineInstr &MI,
72147214
Register Offsets = MI.getOperand(9).getReg();
72157215
Register TDescr = MI.getOperand(10).getReg();
72167216

7217-
if (!ST.hasBVHDualInst()) {
7217+
if (!ST.hasBVHDualAndBVH8Insts()) {
72187218
DiagnosticInfoUnsupported BadIntrin(B.getMF().getFunction(),
72197219
"intrinsic not supported on subtarget",
72207220
MI.getDebugLoc());
72217221
B.getMF().getFunction().getContext().diagnose(BadIntrin);
72227222
return false;
72237223
}
72247224

7225+
bool IsBVH8 = cast<GIntrinsic>(MI).getIntrinsicID() ==
7226+
Intrinsic::amdgcn_image_bvh8_intersect_ray;
72257227
const unsigned NumVDataDwords = 10;
7226-
const unsigned NumVAddrDwords = 12;
7227-
int Opcode = AMDGPU::getMIMGOpcode(AMDGPU::IMAGE_BVH_DUAL_INTERSECT_RAY,
7228-
AMDGPU::MIMGEncGfx12, NumVDataDwords,
7229-
NumVAddrDwords);
7228+
const unsigned NumVAddrDwords = IsBVH8 ? 11 : 12;
7229+
int Opcode = AMDGPU::getMIMGOpcode(
7230+
IsBVH8 ? AMDGPU::IMAGE_BVH8_INTERSECT_RAY
7231+
: AMDGPU::IMAGE_BVH_DUAL_INTERSECT_RAY,
7232+
AMDGPU::MIMGEncGfx12, NumVDataDwords, NumVAddrDwords);
72307233
assert(Opcode != -1);
72317234

72327235
auto RayExtentInstanceMaskVec = B.buildMergeLikeInstr(
72337236
V2S32, {RayExtent, B.buildAnyExt(S32, InstanceMask)});
72347237

7235-
B.buildInstr(AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY)
7238+
B.buildInstr(IsBVH8 ? AMDGPU::G_AMDGPU_BVH8_INTERSECT_RAY
7239+
: AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY)
72367240
.addDef(DstReg)
72377241
.addDef(DstOrigin)
72387242
.addDef(DstDir)
@@ -7598,7 +7602,8 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
75987602
case Intrinsic::amdgcn_image_bvh_intersect_ray:
75997603
return legalizeBVHIntersectRayIntrinsic(MI, B);
76007604
case Intrinsic::amdgcn_image_bvh_dual_intersect_ray:
7601-
return legalizeBVHDualIntrinsic(MI, B);
7605+
case Intrinsic::amdgcn_image_bvh8_intersect_ray:
7606+
return legalizeBVHDualOrBVH8IntersectRayIntrinsic(MI, B);
76027607
case Intrinsic::amdgcn_swmmac_f16_16x16x32_f16:
76037608
case Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16:
76047609
case Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16:

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -208,7 +208,8 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
208208
bool legalizeBVHIntersectRayIntrinsic(MachineInstr &MI,
209209
MachineIRBuilder &B) const;
210210

211-
bool legalizeBVHDualIntrinsic(MachineInstr &MI, MachineIRBuilder &B) const;
211+
bool legalizeBVHDualOrBVH8IntersectRayIntrinsic(MachineInstr &MI,
212+
MachineIRBuilder &B) const;
212213

213214
bool legalizeLaneOp(LegalizerHelper &Helper, MachineInstr &MI,
214215
Intrinsic::ID IID) const;

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 12 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3240,9 +3240,12 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
32403240
return;
32413241
}
32423242
case AMDGPU::G_AMDGPU_BVH_INTERSECT_RAY:
3243+
case AMDGPU::G_AMDGPU_BVH8_INTERSECT_RAY:
32433244
case AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY: {
3244-
bool IsDual = MI.getOpcode() == AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY;
3245-
unsigned NumMods = IsDual ? 0 : 1; // Has A16 modifier
3245+
bool IsDualOrBVH8 =
3246+
MI.getOpcode() == AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY ||
3247+
MI.getOpcode() == AMDGPU::G_AMDGPU_BVH8_INTERSECT_RAY;
3248+
unsigned NumMods = IsDualOrBVH8 ? 0 : 1; // Has A16 modifier
32463249
unsigned LastRegOpIdx = MI.getNumExplicitOperands() - 1 - NumMods;
32473250
applyDefaultMapping(OpdMapper);
32483251
executeInWaterfallLoop(B, MI, {LastRegOpIdx});
@@ -5036,13 +5039,16 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
50365039
return getImageMapping(MRI, MI, RSrcIntrin->RsrcArg);
50375040
}
50385041
case AMDGPU::G_AMDGPU_BVH_INTERSECT_RAY:
5042+
case AMDGPU::G_AMDGPU_BVH8_INTERSECT_RAY:
50395043
case AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY: {
5040-
bool IsDual = MI.getOpcode() == AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY;
5041-
unsigned NumMods = IsDual ? 0 : 1; // Has A16 modifier
5044+
bool IsDualOrBVH8 =
5045+
MI.getOpcode() == AMDGPU::G_AMDGPU_BVH_DUAL_INTERSECT_RAY ||
5046+
MI.getOpcode() == AMDGPU::G_AMDGPU_BVH8_INTERSECT_RAY;
5047+
unsigned NumMods = IsDualOrBVH8 ? 0 : 1; // Has A16 modifier
50425048
unsigned LastRegOpIdx = MI.getNumExplicitOperands() - 1 - NumMods;
50435049
unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
50445050
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, DstSize);
5045-
if (IsDual) {
5051+
if (IsDualOrBVH8) {
50465052
OpdsMapping[1] = AMDGPU::getValueMapping(
50475053
AMDGPU::VGPRRegBankID,
50485054
MRI.getType(MI.getOperand(1).getReg()).getSizeInBits());
@@ -5060,7 +5066,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
50605066
OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
50615067
} else {
50625068
// NSA form
5063-
unsigned FirstSrcOpIdx = IsDual ? 4 : 2;
5069+
unsigned FirstSrcOpIdx = IsDualOrBVH8 ? 4 : 2;
50645070
for (unsigned I = FirstSrcOpIdx; I < LastRegOpIdx; ++I) {
50655071
unsigned Size = MRI.getType(MI.getOperand(I).getReg()).getSizeInBits();
50665072
OpdsMapping[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);

‎llvm/lib/Target/AMDGPU/GCNSubtarget.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -229,7 +229,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
229229
bool HasRestrictedSOffset = false;
230230
bool HasBitOp3Insts = false;
231231
bool HasPrngInst = false;
232-
bool HasBVHDualInst = false;
232+
bool HasBVHDualAndBVH8Insts = false;
233233
bool HasPermlane16Swap = false;
234234
bool HasPermlane32Swap = false;
235235
bool HasVcmpxPermlaneHazard = false;
@@ -1366,7 +1366,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
13661366

13671367
bool hasPrngInst() const { return HasPrngInst; }
13681368

1369-
bool hasBVHDualInst() const { return HasBVHDualInst; }
1369+
bool hasBVHDualAndBVH8Insts() const { return HasBVHDualAndBVH8Insts; }
13701370

13711371
/// Return the maximum number of waves per SIMD for kernels using \p SGPRs
13721372
/// SGPRs

‎llvm/lib/Target/AMDGPU/MIMGInstructions.td

Lines changed: 19 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1509,18 +1509,18 @@ multiclass MIMG_Gather <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0,
15091509
multiclass MIMG_Gather_WQM <mimgopc op, AMDGPUSampleVariant sample>
15101510
: MIMG_Gather<op, sample, 1>;
15111511

1512-
class MIMG_IntersectRay_Helper<bit Is64, bit IsA16, bit isDual> {
1513-
int num_addrs = !if(Is64, !if(IsA16, 9, 12), !if(IsA16, 8, 11));
1512+
class MIMG_IntersectRay_Helper<bit Is64, bit IsA16, bit isDual, bit isBVH8> {
1513+
int num_addrs = !if(isBVH8, 11, !if(Is64, !if(IsA16, 9, 12), !if(IsA16, 8, 11)));
15141514
RegisterClass RegClass = MIMGAddrSize<num_addrs, 0>.RegClass;
15151515
int VAddrDwords = !srl(RegClass.Size, 5);
15161516

15171517
int GFX11PlusNSAAddrs = !if(IsA16, 4, 5);
15181518
RegisterClass node_ptr_type = !if(Is64, VReg_64, VGPR_32);
15191519
list<RegisterClass> GFX11PlusAddrTypes =
1520-
!if(isDual, [VReg_64, VReg_64, VReg_96, VReg_96, VReg_64],
1521-
!if(IsA16,
1522-
[node_ptr_type, VGPR_32, VReg_96, VReg_96],
1523-
[node_ptr_type, VGPR_32, VReg_96, VReg_96, VReg_96]));
1520+
!cond(isBVH8 : [node_ptr_type, VReg_64, VReg_96, VReg_96, VGPR_32],
1521+
isDual : [node_ptr_type, VReg_64, VReg_96, VReg_96, VReg_64],
1522+
IsA16 : [node_ptr_type, VGPR_32, VReg_96, VReg_96],
1523+
true : [node_ptr_type, VGPR_32, VReg_96, VReg_96, VReg_96]);
15241524
}
15251525

15261526
class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC>
@@ -1554,26 +1554,26 @@ class MIMG_IntersectRay_nsa_gfx11<mimgopc op, string opcode, int num_addrs,
15541554
}
15551555

15561556
class VIMAGE_IntersectRay_gfx12<mimgopc op, string opcode, int num_addrs,
1557-
bit isDual,
1557+
bit isDual, bit isBVH8,
15581558
list<RegisterClass> addr_types>
1559-
: VIMAGE_gfx12<op.GFX12, !if(isDual,
1559+
: VIMAGE_gfx12<op.GFX12, !if(!or(isDual, isBVH8),
15601560
(outs VReg_320:$vdata, VReg_96:$ray_origin_out,
15611561
VReg_96:$ray_dir_out),
15621562
(outs VReg_128:$vdata)),
15631563
num_addrs, "GFX12", addr_types> {
1564-
let Constraints = !if(isDual,
1564+
let Constraints = !if(!or(isDual, isBVH8),
15651565
"$ray_origin_out = $vaddr2, $ray_dir_out = $vaddr3", "");
15661566
let InOperandList = !con(nsah.AddrIns, (ins SReg_128_XNULL:$rsrc),
1567-
!if(isDual, (ins), (ins A16:$a16)));
1567+
!if(!or(isDual, isBVH8), (ins), (ins A16:$a16)));
15681568
let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $rsrc"#
1569-
!if(isDual, "", "$a16");
1570-
let SchedRW = !if(isDual,
1569+
!if(!or(isDual, isBVH8), "", "$a16");
1570+
let SchedRW = !if(!or(isDual, isBVH8),
15711571
[WriteVMEM, WriteVMEM, WriteVMEM], [WriteVMEM]);
15721572
}
15731573

15741574
multiclass MIMG_IntersectRay<mimgopc op, string opcode, bit Is64, bit IsA16,
1575-
bit isDual> {
1576-
defvar info = MIMG_IntersectRay_Helper<Is64, IsA16, isDual>;
1575+
bit isDual, bit isBVH8 = 0> {
1576+
defvar info = MIMG_IntersectRay_Helper<Is64, IsA16, isDual, isBVH8>;
15771577
def "" : MIMGBaseOpcode {
15781578
let BVH = 1;
15791579
let A16 = IsA16;
@@ -1611,8 +1611,9 @@ multiclass MIMG_IntersectRay<mimgopc op, string opcode, bit Is64, bit IsA16,
16111611
}
16121612
}
16131613
def _gfx12 : VIMAGE_IntersectRay_gfx12<op, opcode, info.GFX11PlusNSAAddrs,
1614-
isDual, info.GFX11PlusAddrTypes> {
1615-
let VDataDwords = !if(isDual, 10, 4);
1614+
isDual, isBVH8,
1615+
info.GFX11PlusAddrTypes> {
1616+
let VDataDwords = !if(!or(isDual, isBVH8), 10, 4);
16161617
let VAddrDwords = info.num_addrs;
16171618
}
16181619
}
@@ -1791,11 +1792,13 @@ defm IMAGE_BVH64_INTERSECT_RAY_a16 : MIMG_IntersectRay<mimgopc<0x1a, 0x1a, 0xe7>
17911792
} // End OtherPredicates = [HasImageInsts, HasGFX10_AEncoding]
17921793

17931794
defm IMAGE_BVH_DUAL_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0x80, MIMG.NOP, MIMG.NOP>, "image_bvh_dual_intersect_ray", 1, 0, 1>;
1795+
defm IMAGE_BVH8_INTERSECT_RAY : MIMG_IntersectRay<mimgopc<0x81, MIMG.NOP, MIMG.NOP>, "image_bvh8_intersect_ray", 1, 0, 0, 1>;
17941796

17951797
let SubtargetPredicate = isGFX12Plus in {
17961798
def : AMDGPUMnemonicAlias<"bvh_intersect_ray", "image_bvh_intersect_ray">;
17971799
def : AMDGPUMnemonicAlias<"bvh64_intersect_ray", "image_bvh64_intersect_ray">;
17981800
def : AMDGPUMnemonicAlias<"bvh_dual_intersect_ray", "image_bvh_dual_intersect_ray">;
1801+
def : AMDGPUMnemonicAlias<"bvh8_intersect_ray", "image_bvh8_intersect_ray">;
17991802
}
18001803

18011804
} // End let OtherPredicates = [HasImageInsts]

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1387,7 +1387,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
13871387
return true;
13881388
}
13891389
case Intrinsic::amdgcn_image_bvh_dual_intersect_ray:
1390-
case Intrinsic::amdgcn_image_bvh_intersect_ray: {
1390+
case Intrinsic::amdgcn_image_bvh_intersect_ray:
1391+
case Intrinsic::amdgcn_image_bvh8_intersect_ray: {
13911392
Info.opc = ISD::INTRINSIC_W_CHAIN;
13921393
Info.memVT =
13931394
MVT::getVT(IntrID == Intrinsic::amdgcn_image_bvh_intersect_ray
@@ -9443,7 +9444,8 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
94439444
Op->getVTList(), Ops, VT,
94449445
M->getMemOperand());
94459446
}
9446-
case Intrinsic::amdgcn_image_bvh_dual_intersect_ray: {
9447+
case Intrinsic::amdgcn_image_bvh_dual_intersect_ray:
9448+
case Intrinsic::amdgcn_image_bvh8_intersect_ray: {
94479449
MemSDNode *M = cast<MemSDNode>(Op);
94489450
SDValue NodePtr = M->getOperand(2);
94499451
SDValue RayExtent = M->getOperand(3);
@@ -9456,16 +9458,18 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
94569458
assert(NodePtr.getValueType() == MVT::i64);
94579459
assert(RayDir.getValueType() == MVT::v3f32);
94589460

9459-
if (!Subtarget->hasBVHDualInst()) {
9461+
if (!Subtarget->hasBVHDualAndBVH8Insts()) {
94609462
emitRemovedIntrinsicError(DAG, DL, Op.getValueType());
94619463
return SDValue();
94629464
}
94639465

9466+
bool IsBVH8 = IntrID == Intrinsic::amdgcn_image_bvh8_intersect_ray;
94649467
const unsigned NumVDataDwords = 10;
9465-
const unsigned NumVAddrDwords = 12;
9466-
int Opcode = AMDGPU::getMIMGOpcode(AMDGPU::IMAGE_BVH_DUAL_INTERSECT_RAY,
9467-
AMDGPU::MIMGEncGfx12, NumVDataDwords,
9468-
NumVAddrDwords);
9468+
const unsigned NumVAddrDwords = IsBVH8 ? 11 : 12;
9469+
int Opcode = AMDGPU::getMIMGOpcode(
9470+
IsBVH8 ? AMDGPU::IMAGE_BVH8_INTERSECT_RAY
9471+
: AMDGPU::IMAGE_BVH_DUAL_INTERSECT_RAY,
9472+
AMDGPU::MIMGEncGfx12, NumVDataDwords, NumVAddrDwords);
94699473
assert(Opcode != -1);
94709474

94719475
SmallVector<SDValue, 7> Ops;

‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4376,6 +4376,14 @@ def G_AMDGPU_BVH_DUAL_INTERSECT_RAY : AMDGPUGenericInstruction {
43764376
let mayStore = 0;
43774377
}
43784378

4379+
def G_AMDGPU_BVH8_INTERSECT_RAY : AMDGPUGenericInstruction {
4380+
let OutOperandList = (outs type0:$dst, type1:$ray_origin, type1:$ray_dir);
4381+
let InOperandList = (ins unknown:$opcode, variable_ops);
4382+
let hasSideEffects = 0;
4383+
let mayLoad = 1;
4384+
let mayStore = 0;
4385+
}
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// Generic instruction for SI_CALL, so we can select the register bank and insert a waterfall loop
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// if necessary.
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def G_SI_CALL : AMDGPUGenericInstruction {

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