[RISCV] Correctly account for the copy cost of GPR pairs in RISCVMakeCompressible.

Author: topperc

llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp

@@ -332,9 +332,11 @@ static Register analyzeCompressibleUses(MachineInstr &FirstMI,
   // are required for a code size reduction. If no base adjustment is required,
   // then copying the register costs one new c.mv (or c.li Rd, 0 for "copying"
   // the zero register) and therefore two uses are required for a code size
-  // reduction.
-  if (MIs.size() < 2 || (RegImm.Imm != 0 && MIs.size() < 3))
-    return RISCV::NoRegister;
+  // reduction. For GPR pairs, we need 2 ADDIs to copy so we need three users.
+  unsigned CopyCost = RISCV::GPRPairRegClass.contains(RegImm.Reg) ? 2 : 1;
+  assert((RegImm.Imm == 0 || CopyCost == 1) && "GPRPair should have zero imm");
+  if (MIs.size() <= CopyCost || (RegImm.Imm != 0 && MIs.size() <= 2))
+    return Register();
 
   // Find a compressible register which will be available from the first
   // instruction we care about to the last.

llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir

@@ -234,10 +234,8 @@ body:             |
     ; RV32-LABEL: name: store_common_value_double_no_opt2
     ; RV32: liveins: $x10, $x16, $x17
     ; RV32-NEXT: {{  $}}
-    ; RV32-NEXT: $x12 = ADDI $x16, 0
-    ; RV32-NEXT: $x13 = ADDI $x17, 0
-    ; RV32-NEXT: SD_RV32 $x12_x13, renamable $x10, 0 :: (volatile store (s64) into %ir.a)
-    ; RV32-NEXT: SD_RV32 killed $x12_x13, killed renamable $x10, 0 :: (volatile store (s64) into %ir.a)
+    ; RV32-NEXT: SD_RV32 renamable $x16_x17, renamable $x10, 0 :: (volatile store (s64) into %ir.a)
+    ; RV32-NEXT: SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (volatile store (s64) into %ir.a)
     ; RV32-NEXT: PseudoRET
     SD_RV32 renamable $x16_x17, renamable $x10, 0 :: (volatile store (s64) into %ir.a)
     SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (volatile store (s64) into %ir.a)