[clang][docs] Release Note for RISC-V qci-(no)nest

These were omitted from the original PR (#129957)

Author: lenary

clang/docs/ReleaseNotes.rst

@@ -425,6 +425,11 @@ RISC-V Support
 
 - Add support for `-mtune=generic-ooo` (a generic out-of-order model).
 
+- Adds support for `__attribute__((interrupt("qci-nest")))` and
+  `__attribute__((interrupt("qci-nonest")))`. These use instructions from
+  Qualcomm's `Xqciint` extension to save and restore some GPRs in interrupt
+  service routines.
+
 CUDA/HIP Language Changes
 ^^^^^^^^^^^^^^^^^^^^^^^^^
 

llvm/docs/ReleaseNotes.md

@@ -147,6 +147,9 @@ Changes to the RISC-V Backend
 * Adds assembler support for the 'Zclsd` (Compressed Load/Store Pair Instructions)
   extension.
 * Adds experimental assembler support for Zvqdotq.
+* Adds Support for Qualcomm's `qci-nest` and `qci-nonest` interrupt types, which
+  use instructions from `Xqciint` to save and restore some GPRs during interrupt
+  handlers.
 
 Changes to the WebAssembly Backend
 ----------------------------------