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AMDGPU: Add baseline test for gws handling with AGPR inputs (#169372)
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‎llvm/test/CodeGen/AMDGPU/gws_agpr.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=CHECK,SDAG %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=CHECK,GISEL %s
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define void @gws_init_offset0() #0 {
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; SDAG-LABEL: gws_init_offset0:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: ;;#ASMSTART
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; SDAG-NEXT: ; def a0
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; SDAG-NEXT: ;;#ASMEND
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; SDAG-NEXT: s_mov_b32 m0, 0
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; SDAG-NEXT: s_nop 0
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; SDAG-NEXT: ds_gws_init a0 gds
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: gws_init_offset0:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; def a0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: v_accvgpr_read_b32 v0, a0
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; GISEL-NEXT: s_mov_b32 m0, 0
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; GISEL-NEXT: s_nop 0
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; GISEL-NEXT: ds_gws_init v0 gds
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%val = call i32 asm "; def $0", "=a"()
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call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 0)
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ret void
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}
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define void @gws_init_offset63() #0 {
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; SDAG-LABEL: gws_init_offset63:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: ;;#ASMSTART
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; SDAG-NEXT: ; def a0
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; SDAG-NEXT: ;;#ASMEND
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; SDAG-NEXT: s_mov_b32 m0, 0
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; SDAG-NEXT: s_nop 0
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; SDAG-NEXT: ds_gws_init a0 offset:63 gds
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: gws_init_offset63:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; def a0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: v_accvgpr_read_b32 v0, a0
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; GISEL-NEXT: s_mov_b32 m0, 0
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; GISEL-NEXT: s_nop 0
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; GISEL-NEXT: ds_gws_init v0 offset:63 gds
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%val = call i32 asm "; def $0", "=a"()
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call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 63)
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ret void
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}
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define void @gws_init_sgpr_offset(i32 inreg %offset) #0 {
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; SDAG-LABEL: gws_init_sgpr_offset:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: ;;#ASMSTART
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; SDAG-NEXT: ; def a0
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; SDAG-NEXT: ;;#ASMEND
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; SDAG-NEXT: s_lshl_b32 m0, s16, 16
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; SDAG-NEXT: s_nop 0
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; SDAG-NEXT: ds_gws_init a0 gds
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: gws_init_sgpr_offset:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; def a0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: v_accvgpr_read_b32 v0, a0
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; GISEL-NEXT: s_lshl_b32 m0, s16, 16
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; GISEL-NEXT: s_nop 0
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; GISEL-NEXT: ds_gws_init v0 gds
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%val = call i32 asm "; def $0", "=a"()
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call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset)
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ret void
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}
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define amdgpu_kernel void @gws_init_agpr_offset() #0 {
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; SDAG-LABEL: gws_init_agpr_offset:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: ;;#ASMSTART
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; SDAG-NEXT: ; def a1
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; SDAG-NEXT: ;;#ASMEND
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; SDAG-NEXT: v_accvgpr_read_b32 v0, a1
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; SDAG-NEXT: v_readfirstlane_b32 s0, v0
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; SDAG-NEXT: ;;#ASMSTART
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; SDAG-NEXT: ; def a0
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; SDAG-NEXT: ;;#ASMEND
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; SDAG-NEXT: s_lshl_b32 m0, s0, 16
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; SDAG-NEXT: s_nop 0
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; SDAG-NEXT: ds_gws_init a0 gds
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_endpgm
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;
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; GISEL-LABEL: gws_init_agpr_offset:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; def a1
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: v_accvgpr_read_b32 v0, a1
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; GISEL-NEXT: v_readfirstlane_b32 s0, v0
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; def a0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: v_accvgpr_read_b32 v2, a0
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; GISEL-NEXT: s_lshl_b32 m0, s0, 16
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; GISEL-NEXT: s_nop 0
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; GISEL-NEXT: ds_gws_init v2 gds
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: s_endpgm
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%val = call i32 asm "; def $0", "=a"()
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%offset = call i32 asm "; def $0", "=a"()
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call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset)
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ret void
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}
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define void @gws_init_agpr_offset_add1() #0 {
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; SDAG-LABEL: gws_init_agpr_offset_add1:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: ;;#ASMSTART
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; SDAG-NEXT: ; def a1
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; SDAG-NEXT: ;;#ASMEND
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; SDAG-NEXT: v_accvgpr_read_b32 v0, a1
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; SDAG-NEXT: v_readfirstlane_b32 s4, v0
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; SDAG-NEXT: ;;#ASMSTART
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; SDAG-NEXT: ; def a0
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; SDAG-NEXT: ;;#ASMEND
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; SDAG-NEXT: s_lshl_b32 m0, s4, 16
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; SDAG-NEXT: s_nop 0
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; SDAG-NEXT: ds_gws_init a0 offset:1 gds
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: gws_init_agpr_offset_add1:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; def a1
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: v_accvgpr_read_b32 v0, a1
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; GISEL-NEXT: v_readfirstlane_b32 s4, v0
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; def a0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: v_accvgpr_read_b32 v2, a0
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; GISEL-NEXT: s_lshl_b32 m0, s4, 16
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; GISEL-NEXT: s_nop 0
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; GISEL-NEXT: ds_gws_init v2 offset:1 gds
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%val = call i32 asm "; def $0", "=a"()
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%offset.base = call i32 asm "; def $0", "=a"()
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%offset = add i32 %offset.base, 1
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call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset)
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ret void
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}
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define amdgpu_kernel void @gws_init_vgpr_offset_add(i32 %val) #0 {
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; CHECK-LABEL: gws_init_vgpr_offset_add:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dword s0, s[8:9], 0x0
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def a0
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_accvgpr_read_b32 v0, a0
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; CHECK-NEXT: v_readfirstlane_b32 s1, v0
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; CHECK-NEXT: s_lshl_b32 m0, s1, 16
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: ds_gws_init v0 offset:3 gds
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_endpgm
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%agpr.offset.base = call i32 asm "; def $0", "=a"()
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%agpr.offset = add i32 %agpr.offset.base, 3
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call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %agpr.offset)
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ret void
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}
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define void @gws_barrier_offset0() #0 {
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; SDAG-LABEL: gws_barrier_offset0:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: ;;#ASMSTART
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; SDAG-NEXT: ; def a0
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; SDAG-NEXT: ;;#ASMEND
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; SDAG-NEXT: s_mov_b32 m0, 0
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; SDAG-NEXT: s_nop 0
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; SDAG-NEXT: ds_gws_barrier a0 gds
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: gws_barrier_offset0:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; def a0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: v_accvgpr_read_b32 v0, a0
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; GISEL-NEXT: s_mov_b32 m0, 0
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; GISEL-NEXT: s_nop 0
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; GISEL-NEXT: ds_gws_barrier v0 gds
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%val = call i32 asm "; def $0", "=a"()
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 0)
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ret void
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}
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define void @gws_barrier_offset63() #0 {
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; SDAG-LABEL: gws_barrier_offset63:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: ;;#ASMSTART
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; SDAG-NEXT: ; def a0
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; SDAG-NEXT: ;;#ASMEND
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; SDAG-NEXT: s_mov_b32 m0, 0
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; SDAG-NEXT: s_nop 0
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; SDAG-NEXT: ds_gws_barrier a0 offset:63 gds
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: gws_barrier_offset63:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; def a0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: v_accvgpr_read_b32 v0, a0
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; GISEL-NEXT: s_mov_b32 m0, 0
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; GISEL-NEXT: s_nop 0
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; GISEL-NEXT: ds_gws_barrier v0 offset:63 gds
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%val = call i32 asm "; def $0", "=a"()
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 63)
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ret void
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}
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define void @gws_barrier_sgpr_offset(i32 inreg %offset) #0 {
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; SDAG-LABEL: gws_barrier_sgpr_offset:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: ;;#ASMSTART
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; SDAG-NEXT: ; def a0
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; SDAG-NEXT: ;;#ASMEND
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; SDAG-NEXT: s_lshl_b32 m0, s16, 16
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; SDAG-NEXT: s_nop 0
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; SDAG-NEXT: ds_gws_barrier a0 gds
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: gws_barrier_sgpr_offset:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; def a0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: v_accvgpr_read_b32 v0, a0
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; GISEL-NEXT: s_lshl_b32 m0, s16, 16
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; GISEL-NEXT: s_nop 0
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; GISEL-NEXT: ds_gws_barrier v0 gds
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%val = call i32 asm "; def $0", "=a"()
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 %offset)
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ret void
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}
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define void @gws_sema_v_offset0() #0 {
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; SDAG-LABEL: gws_sema_v_offset0:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_mov_b32 m0, 0
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; SDAG-NEXT: s_nop 0
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; SDAG-NEXT: ds_gws_sema_v gds
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: gws_sema_v_offset0:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: s_mov_b32 m0, 0
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; GISEL-NEXT: s_nop 0
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; GISEL-NEXT: ds_gws_sema_v gds
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; def a0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%val = call i32 asm "; def $0", "=a"()
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call void @llvm.amdgcn.ds.gws.sema.v(i32 0)
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ret void
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}
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define void @gws_sema_br_offset0() #0 {
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; SDAG-LABEL: gws_sema_br_offset0:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: ;;#ASMSTART
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; SDAG-NEXT: ; def a0
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; SDAG-NEXT: ;;#ASMEND
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; SDAG-NEXT: s_mov_b32 m0, 0
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; SDAG-NEXT: s_nop 0
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; SDAG-NEXT: ds_gws_sema_br a0 gds
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: gws_sema_br_offset0:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; def a0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: v_accvgpr_read_b32 v0, a0
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; GISEL-NEXT: s_mov_b32 m0, 0
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; GISEL-NEXT: s_nop 0
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; GISEL-NEXT: ds_gws_sema_br v0 gds
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%val = call i32 asm "; def $0", "=a"()
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call void @llvm.amdgcn.ds.gws.sema.br(i32 %val, i32 0)
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ret void
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}
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define void @gws_sema_p_offset0() #0 {
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; SDAG-LABEL: gws_sema_p_offset0:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_mov_b32 m0, 0
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; SDAG-NEXT: s_nop 0
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; SDAG-NEXT: ds_gws_sema_p gds
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: gws_sema_p_offset0:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: s_mov_b32 m0, 0
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; GISEL-NEXT: s_nop 0
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; GISEL-NEXT: ds_gws_sema_p gds
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; def a0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%val = call i32 asm "; def $0", "=a"()
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call void @llvm.amdgcn.ds.gws.sema.p(i32 0)
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ret void
367+
}
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define void @gws_sema_release_all_offset0() #0 {
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; SDAG-LABEL: gws_sema_release_all_offset0:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_mov_b32 m0, 0
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; SDAG-NEXT: s_nop 0
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; SDAG-NEXT: ds_gws_sema_release_all gds
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: gws_sema_release_all_offset0:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: s_mov_b32 m0, 0
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; GISEL-NEXT: s_nop 0
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; GISEL-NEXT: ds_gws_sema_release_all gds
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; def a0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%val = call i32 asm "; def $0", "=a"()
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call void @llvm.amdgcn.ds.gws.sema.release.all(i32 0)
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ret void
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}
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attributes #0 = { nounwind }

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