!fixup address comments

Author: juliannagele

llvm/lib/Transforms/Vectorize/VectorCombine.cpp

@@ -1856,20 +1856,19 @@ bool VectorCombine::scalarizeLoad(Instruction &I) {
 
   auto *LI = cast<LoadInst>(&I);
   auto *VecTy = cast<VectorType>(LI->getType());
-  if (!VecTy || LI->isVolatile() ||
-      !DL->typeSizeEqualsStoreSize(VecTy->getScalarType()))
+  if (LI->isVolatile() || !DL->typeSizeEqualsStoreSize(VecTy->getScalarType()))
     return false;
 
-  // Check what type of users we have and ensure no memory modifications betwwen
-  // the load and its users.
   bool AllExtracts = true;
   bool AllBitcasts = true;
   Instruction *LastCheckedInst = LI;
   unsigned NumInstChecked = 0;
 
+  // Check what type of users we have and ensure no memory modifications betwwen
+  // the load and its users.
   for (User *U : LI->users()) {
     auto *UI = dyn_cast<Instruction>(U);
-    if (!UI || UI->getParent() != LI->getParent() || UI->use_empty())
+    if (!UI || UI->getParent() != LI->getParent())
       return false;
 
     // If any user is waiting to be erased, then bail out as this will
@@ -1909,18 +1908,18 @@ bool VectorCombine::scalarizeLoadExtract(LoadInst *LI, VectorType *VecTy,
   if (!TTI.allowVectorElementIndexingUsingGEP())
     return false;
 
-  InstructionCost OriginalCost =
-      TTI.getMemoryOpCost(Instruction::Load, VecTy, LI->getAlign(),
-                          LI->getPointerAddressSpace(), CostKind);
-  InstructionCost ScalarizedCost = 0;
-
   DenseMap<ExtractElementInst *, ScalarizationResult> NeedFreeze;
   auto FailureGuard = make_scope_exit([&]() {
     // If the transform is aborted, discard the ScalarizationResults.
     for (auto &Pair : NeedFreeze)
       Pair.second.discard();
   });
 
+  InstructionCost OriginalCost =
+      TTI.getMemoryOpCost(Instruction::Load, VecTy, LI->getAlign(),
+                          LI->getPointerAddressSpace(), CostKind);
+  InstructionCost ScalarizedCost = 0;
+
   for (User *U : LI->users()) {
     auto *UI = cast<ExtractElementInst>(U);
 
@@ -2011,7 +2010,7 @@ bool VectorCombine::scalarizeLoadBitcast(LoadInst *LI, VectorType *VecTy,
     if (DestBitWidth != VecBitWidth)
       return false;
 
-    // All bitcasts should target the same scalar type.
+    // All bitcasts must target the same scalar type.
     if (!TargetScalarType)
       TargetScalarType = DestTy;
     else if (TargetScalarType != DestTy)
@@ -2024,6 +2023,7 @@ bool VectorCombine::scalarizeLoadBitcast(LoadInst *LI, VectorType *VecTy,
 
   if (!TargetScalarType)
     return false;
+
   assert(!LI->user_empty() && "Unexpected load without bitcast users");
   InstructionCost ScalarizedCost =
       TTI.getMemoryOpCost(Instruction::Load, TargetScalarType, LI->getAlign(),

llvm/test/Transforms/VectorCombine/AArch64/load-ext-extract.ll renamed to llvm/test/Transforms/PhaseOrdering/AArch64/scalarize-load-ext-extract.ll

@@ -1,9 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -passes=vector-combine,dce,vector-combine -mtriple=arm64-apple-darwinos -S %s | FileCheck %s
+; RUN: opt -O3 -mtriple=arm64-apple-darwinos -S %s | FileCheck %s
 
 define noundef i32 @load_ext_extract(ptr %src) {
-; CHECK-LABEL: define noundef i32 @load_ext_extract(
-; CHECK-SAME: ptr [[SRC:%.*]]) {
+; CHECK-LABEL: define noundef range(i32 0, 1021) i32 @load_ext_extract(
+; CHECK-SAME: ptr readonly captures(none) [[SRC:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
 ; CHECK-NEXT:  [[ENTRY:.*:]]
 ; CHECK-NEXT:    [[TMP14:%.*]] = load i32, ptr [[SRC]], align 4
 ; CHECK-NEXT:    [[TMP15:%.*]] = lshr i32 [[TMP14]], 24
@@ -12,9 +12,9 @@ define noundef i32 @load_ext_extract(ptr %src) {
 ; CHECK-NEXT:    [[TMP18:%.*]] = lshr i32 [[TMP14]], 8
 ; CHECK-NEXT:    [[TMP19:%.*]] = and i32 [[TMP18]], 255
 ; CHECK-NEXT:    [[TMP20:%.*]] = and i32 [[TMP14]], 255
-; CHECK-NEXT:    [[ADD1:%.*]] = add i32 [[TMP20]], [[TMP19]]
-; CHECK-NEXT:    [[ADD2:%.*]] = add i32 [[ADD1]], [[TMP17]]
-; CHECK-NEXT:    [[ADD3:%.*]] = add i32 [[ADD2]], [[TMP15]]
+; CHECK-NEXT:    [[ADD1:%.*]] = add nuw nsw i32 [[TMP20]], [[TMP19]]
+; CHECK-NEXT:    [[ADD2:%.*]] = add nuw nsw i32 [[ADD1]], [[TMP17]]
+; CHECK-NEXT:    [[ADD3:%.*]] = add nuw nsw i32 [[ADD2]], [[TMP15]]
 ; CHECK-NEXT:    ret i32 [[ADD3]]
 ;
 entry: