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[X86] Truncate i64 sub to i32 when upper 33 bits are zeros
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‎llvm/lib/Target/X86/X86ISelLowering.cpp‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58064,8 +58064,28 @@ static SDValue combineSub(SDNode *N, SelectionDAG &DAG,
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EVT VT = N->getValueType(0);
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SDValue Op0 = N->getOperand(0);
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SDValue Op1 = N->getOperand(1);
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unsigned int Opcode = N->getOpcode();
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SDLoc DL(N);
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// Use a 32-bit sub+zext if upper 33 bits known zero.
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if (VT == MVT::i64 && Subtarget.is64Bit()) {
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APInt HiMask = APInt::getHighBitsSet(64, 33);
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if (DAG.MaskedValueIsZero(Op0, HiMask) &&
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DAG.MaskedValueIsZero(Op1, HiMask)) {
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SDValue LHS = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op0);
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SDValue RHS = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
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bool NUW = Op0->getFlags().hasNoUnsignedWrap();
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NUW = NUW & DAG.willNotOverflowAdd(false, LHS, RHS);
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SDNodeFlags Flags;
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Flags.setNoUnsignedWrap(NUW);
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// Always true since in the worst case 0 - 2147483647 = -2147483647, still
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// fits in i32
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Flags.setNoSignedWrap(true);
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SDValue Sub = DAG.getNode(Opcode, DL, MVT::i32, LHS, RHS, Flags);
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return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Sub);
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}
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}
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auto IsNonOpaqueConstant = [&](SDValue Op) {
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return DAG.isConstantIntBuildVectorOrConstantInt(Op,
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/*AllowOpaques*/ false);

‎llvm/test/CodeGen/X86/reduce-i64-sub-vector.ll‎

Lines changed: 98 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,98 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse | FileCheck %s --check-prefixes=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX2
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define <2 x i64> @test1(ptr%ptr) {
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; SSE-LABEL: test1:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: movzbl (%rdi), %eax
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; SSE-NEXT: movzbl %al, %ecx
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; SSE-NEXT: shrb %al
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; SSE-NEXT: movzbl %al, %eax
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; SSE-NEXT: negl %eax
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; SSE-NEXT: movd %eax, %xmm1
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; SSE-NEXT: andl $1, %ecx
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; SSE-NEXT: negl %ecx
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; SSE-NEXT: movd %ecx, %xmm0
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; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE-NEXT: retq
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;
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; SSE2-LABEL: test1:
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; SSE2: # %bb.0: # %entry
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; SSE2-NEXT: movzbl (%rdi), %eax
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; SSE2-NEXT: movzbl %al, %ecx
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; SSE2-NEXT: shrb %al
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; SSE2-NEXT: movzbl %al, %eax
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; SSE2-NEXT: negl %eax
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; SSE2-NEXT: movd %eax, %xmm1
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; SSE2-NEXT: andl $1, %ecx
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; SSE2-NEXT: negl %ecx
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; SSE2-NEXT: movd %ecx, %xmm0
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: test1:
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; SSSE3: # %bb.0: # %entry
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; SSSE3-NEXT: movzbl (%rdi), %eax
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; SSSE3-NEXT: movzbl %al, %ecx
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; SSSE3-NEXT: shrb %al
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; SSSE3-NEXT: movzbl %al, %eax
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; SSSE3-NEXT: negl %eax
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; SSSE3-NEXT: movd %eax, %xmm1
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; SSSE3-NEXT: andl $1, %ecx
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; SSSE3-NEXT: negl %ecx
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; SSSE3-NEXT: movd %ecx, %xmm0
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: test1:
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; SSE41: # %bb.0: # %entry
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; SSE41-NEXT: movzbl (%rdi), %eax
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; SSE41-NEXT: movzbl %al, %ecx
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; SSE41-NEXT: shrb %al
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; SSE41-NEXT: movzbl %al, %eax
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; SSE41-NEXT: negl %eax
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; SSE41-NEXT: movd %eax, %xmm1
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; SSE41-NEXT: andl $1, %ecx
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; SSE41-NEXT: negl %ecx
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; SSE41-NEXT: movd %ecx, %xmm0
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; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: test1:
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; AVX1: # %bb.0: # %entry
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; AVX1-NEXT: movzbl (%rdi), %eax
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; AVX1-NEXT: movzbl %al, %ecx
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; AVX1-NEXT: shrb %al
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; AVX1-NEXT: movzbl %al, %eax
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; AVX1-NEXT: negl %eax
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; AVX1-NEXT: vmovd %eax, %xmm0
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; AVX1-NEXT: andl $1, %ecx
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; AVX1-NEXT: negl %ecx
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; AVX1-NEXT: vmovd %ecx, %xmm1
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; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test1:
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; AVX2: # %bb.0: # %entry
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; AVX2-NEXT: movzbl (%rdi), %eax
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; AVX2-NEXT: movzbl %al, %ecx
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; AVX2-NEXT: shrb %al
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; AVX2-NEXT: movzbl %al, %eax
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; AVX2-NEXT: negl %eax
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; AVX2-NEXT: vmovd %eax, %xmm0
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; AVX2-NEXT: andl $1, %ecx
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; AVX2-NEXT: negl %ecx
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; AVX2-NEXT: vmovd %ecx, %xmm1
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; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
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; AVX2-NEXT: retq
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entry:
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%X = load <2 x i1>, ptr %ptr
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%Y = sext <2 x i1> %X to <2 x i64>
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ret <2 x i64> %Y
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}
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‎llvm/test/CodeGen/X86/reduce-i64-sub.ll‎

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,96 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -disable-cgp-branch-opts | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -disable-cgp-branch-opts | FileCheck %s --check-prefix=X64
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; Truncate to 32 bit subtraction since first 48 bits are zeros
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define i64 @test1(i16 %a, i16 %b) nounwind {
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; X86-LABEL: test1:
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; X86: # %bb.0:
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; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: xorl %edx, %edx
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; X86-NEXT: subl %ecx, %eax
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; X86-NEXT: sbbl %edx, %edx
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; X86-NEXT: retl
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;
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; X64-LABEL: test1:
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; X64: # %bb.0:
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; X64-NEXT: movzwl %si, %ecx
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; X64-NEXT: movzwl %di, %eax
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; X64-NEXT: subl %ecx, %eax
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; X64-NEXT: retq
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%zext_a = zext i16 %a to i64
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%zext_b = zext i16 %b to i64
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%sub = sub i64 %zext_a, %zext_b
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ret i64 %sub
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}
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; Do not truncate to 32 bit subtraction if 32nd bit is set
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define i64 @test2(i16 %a, i16 %b) nounwind {
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; X86-LABEL: test2:
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; X86: # %bb.0:
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; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: subl %ecx, %eax
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; X86-NEXT: movl $1, %edx
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; X86-NEXT: sbbl $0, %edx
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; X86-NEXT: retl
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;
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; X64-LABEL: test2:
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; X64: # %bb.0:
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; X64-NEXT: movzwl %di, %ecx
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; X64-NEXT: movzwl %si, %edx
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; X64-NEXT: movabsq $4294967296, %rax # imm = 0x100000000
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; X64-NEXT: orq %rcx, %rax
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; X64-NEXT: subq %rdx, %rax
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; X64-NEXT: retq
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%zext_a = zext i16 %a to i64
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%zext_b = zext i16 %b to i64
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%or_a = or i64 %zext_a, 4294967296
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%sub = sub i64 %or_a, %zext_b
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ret i64 %sub
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}
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; Do not truncate to 32 bit subtraction in case of sign extension
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define i64 @test3(i16 %a, i16 %b) nounwind {
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; X86-LABEL: test3:
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; X86: # %bb.0:
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; X86-NEXT: movswl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl %eax, %edx
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; X86-NEXT: sarl $31, %edx
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; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: subl %ecx, %eax
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; X86-NEXT: sbbl $0, %edx
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; X86-NEXT: retl
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;
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; X64-LABEL: test3:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-NEXT: movswq %di, %rax
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; X64-NEXT: movzwl %si, %ecx
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; X64-NEXT: subq %rcx, %rax
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; X64-NEXT: retq
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%sext_a = sext i16 %a to i64
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%zext_b = zext i16 %b to i64
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%sub = sub i64 %sext_a, %zext_b
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ret i64 %sub
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}
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define i64 @test4(i16 %x) nounwind {
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; X86-LABEL: test4:
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; X86: # %bb.0:
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; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: xorl %edx, %edx
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; X86-NEXT: negl %eax
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; X86-NEXT: sbbl %edx, %edx
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; X86-NEXT: retl
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;
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; X64-LABEL: test4:
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; X64: # %bb.0:
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; X64-NEXT: movzwl %di, %eax
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; X64-NEXT: negl %eax
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; X64-NEXT: retq
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%zext_x = zext i16 %x to i64
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%sub = sub i64 0, %zext_x
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ret i64 %sub
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}

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