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[Xtensa] Fix tests comments.
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‎llvm/test/MC/Disassembler/Xtensa/windowed.txt‎

Lines changed: 33 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1,72 +1,71 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
12
# RUN: llvm-mc -triple=xtensa -mattr=+windowed -disassemble %s | FileCheck -check-prefixes=CHECK-WINDOWED %s
23
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
34

4-
#------------------------------------------------------------------------------
5-
# Verify that binary code is correctly disassembled with
6-
# windowed register option enabled. Also verify that dissasembling without
7-
# windowed register option generates warnings.
8-
#------------------------------------------------------------------------------
5+
## Verify that binary code is correctly disassembled with
6+
## windowed register option enabled. Also verify that dissasembling without
7+
## windowed register option generates warnings.
98

109
[0x36,0x03,0x01]
11-
# CHECK-WINDOWED: entry a3, 128
12-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
10+
# CHECK-WINDOWED: entry a3, 128
11+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
1312

1413
[0x30,0x14,0x00]
15-
# CHECK-WINDOWED: movsp a3, a4
16-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
14+
# CHECK-WINDOWED: movsp a3, a4
15+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
1716

1817
[0x15,0x10,0x00]
19-
# CHECK-WINDOWED: call4 . +260
20-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
18+
# CHECK-WINDOWED: call4 . +260
19+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
2120

2221
[0x25,0x10,0x00]
23-
# CHECK-WINDOWED: call8 . +260
24-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
22+
# CHECK-WINDOWED: call8 . +260
23+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
2524

2625
[0x35,0x10,0x00]
27-
# CHECK-WINDOWED: call12 . +260
28-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
26+
# CHECK-WINDOWED: call12 . +260
27+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
2928

3029
[0xd0,0x03,0x00]
31-
# CHECK-WINDOWED: callx4 a3
32-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
30+
# CHECK-WINDOWED: callx4 a3
31+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
3332

3433
[0xe0,0x03,0x00]
35-
# CHECK-WINDOWED: callx8 a3
36-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
34+
# CHECK-WINDOWED: callx8 a3
35+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
3736

3837
[0xf0,0x03,0x00]
39-
# CHECK-WINDOWED: callx12 a3
40-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
38+
# CHECK-WINDOWED: callx12 a3
39+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
4140

4241
[0x90,0x00,0x00]
4342
# CHECK-WINDOWED: retw
44-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
43+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
4544

4645
[0x20,0x80,0x40]
47-
# CHECK-WINDOWED: rotw 2
48-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
46+
# CHECK-WINDOWED: rotw 2
47+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
4948

5049
[0x30,0xd4,0x09]
51-
# CHECK-WINDOWED: l32e a3, a4, -12
52-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
50+
# CHECK-WINDOWED: l32e a3, a4, -12
51+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
5352

5453
[0x30,0xd4,0x49]
55-
# CHECK-WINDOWED: s32e a3, a4, -12
56-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
54+
# CHECK-WINDOWED: s32e a3, a4, -12
55+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
5756

5857
[0x00,0x34,0x00]
5958
# CHECK-WINDOWED: rfwo
60-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
59+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
6160

6261
[0x00,0x35,0x00]
6362
# CHECK-WINDOWED: rfwu
64-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
63+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
6564

6665
[0x30,0x48,0x61]
67-
# CHECK-WINDOWED: xsr a3, windowbase
68-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
66+
# CHECK-WINDOWED: xsr a3, windowbase
67+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding
6968

7069
[0x30,0x49,0x61]
71-
# CHECK-WINDOWED: xsr a3, windowstart
72-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
70+
# CHECK-WINDOWED: xsr a3, windowstart
71+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding

‎llvm/test/MC/Disassembler/Xtensa/windowed_code_density.txt‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,11 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
12
# RUN: llvm-mc -triple=xtensa -mattr=+windowed,+density -disassemble %s | FileCheck -check-prefixes=CHECK-WINDOWED-DENSITY %s
23
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
34

4-
#------------------------------------------------------------------------------
5-
# Verify that binary code is correctly disassembled with windowed register
6-
# and code density options enabled. Also verify that
7-
# dissasembling without these options generates warnings.
8-
#------------------------------------------------------------------------------
5+
## Verify that binary code is correctly disassembled with windowed register
6+
## and code density options enabled. Also verify that
7+
## dissasembling without these options generates warnings.
98

109
[0x1d,0xf0]
1110
# CHECK-WINDOWED-DENSITY: retw.n
12-
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
11+
# CHECK-CORE: :[[@LINE-2]]:2: warning: invalid instruction encoding

‎llvm/test/MC/Xtensa/windowed_invalid.s‎

Lines changed: 18 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,23 +1,35 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
12
# RUN: not llvm-mc -triple xtensa --mattr=+windowed %s 2>&1 | FileCheck %s
23

3-
# Out of range immediates
4+
## Out of range immediates
5+
46

57
# entry_imm12
8+
9+
610
entry a3, -1
7-
# CHECK: :[[#@LINE-1]]:11: error: expected immediate in range [0, 32760], first 3 bits should be zero
11+
// CHECK: :[[@LINE-1]]:11: error: expected immediate in range [0, 32760], first 3 bits should be zero
812

913
# entry_imm12
14+
15+
1016
entry a3, 32764
11-
# CHECK: :[[#@LINE-1]]:11: error: expected immediate in range [0, 32760], first 3 bits should be zero
17+
// CHECK: :[[@LINE-1]]:11: error: expected immediate in range [0, 32760], first 3 bits should be zero
1218

1319
# entry_imm12
20+
21+
1422
entry a3, 4
15-
# CHECK: :[[#@LINE-1]]:11: error: expected immediate in range [0, 32760], first 3 bits should be zero
23+
// CHECK: :[[@LINE-1]]:11: error: expected immediate in range [0, 32760], first 3 bits should be zero
1624

1725
# imm8n_7
26+
27+
1828
rotw 100
19-
# CHECK: :[[#@LINE-1]]:6: error: expected immediate in range [-8, 7]
29+
// CHECK: :[[@LINE-1]]:6: error: expected immediate in range [-8, 7]
2030

2131
# imm64n_4n
32+
33+
2234
l32e a3, a4, -100
23-
# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [-64, -4]
35+
// CHECK: :[[@LINE-1]]:14: error: expected immediate in range [-64, -4]

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