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[LoongArch] Optimize vreplgr2vr + vinsgr2vr intrinsic sequence (#115803)
Inspired by #101624.
1 parent 3c585bd commit 512208b

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6 files changed

+33
-41
lines changed

6 files changed

+33
-41
lines changed

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4229,11 +4229,10 @@ performINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
42294229
case Intrinsic::loongarch_lasx_xvreplgr2vr_b:
42304230
case Intrinsic::loongarch_lasx_xvreplgr2vr_h:
42314231
case Intrinsic::loongarch_lasx_xvreplgr2vr_w:
4232-
case Intrinsic::loongarch_lasx_xvreplgr2vr_d: {
4233-
EVT ResTy = N->getValueType(0);
4234-
SmallVector<SDValue> Ops(ResTy.getVectorNumElements(), N->getOperand(1));
4235-
return DAG.getBuildVector(ResTy, DL, Ops);
4236-
}
4232+
case Intrinsic::loongarch_lasx_xvreplgr2vr_d:
4233+
return DAG.getNode(LoongArchISD::VREPLGR2VR, DL, N->getValueType(0),
4234+
DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getGRLenVT(),
4235+
N->getOperand(1)));
42374236
case Intrinsic::loongarch_lsx_vreplve_b:
42384237
case Intrinsic::loongarch_lsx_vreplve_h:
42394238
case Intrinsic::loongarch_lsx_vreplve_w:
@@ -4710,6 +4709,7 @@ const char *LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
47104709
NODE_NAME_CASE(VILVH)
47114710
NODE_NAME_CASE(VSHUF4I)
47124711
NODE_NAME_CASE(VREPLVEI)
4712+
NODE_NAME_CASE(VREPLGR2VR)
47134713
NODE_NAME_CASE(XVPERMI)
47144714
NODE_NAME_CASE(VPICK_SEXT_ELT)
47154715
NODE_NAME_CASE(VPICK_ZEXT_ELT)

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -129,6 +129,7 @@ enum NodeType : unsigned {
129129
VILVH,
130130
VSHUF4I,
131131
VREPLVEI,
132+
VREPLGR2VR,
132133
XVPERMI,
133134

134135
// Extended vector element extraction

‎llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1574,6 +1574,15 @@ def : Pat<(lasxsplati16 GPR:$rj), (XVREPLGR2VR_H GPR:$rj)>;
15741574
def : Pat<(lasxsplati32 GPR:$rj), (XVREPLGR2VR_W GPR:$rj)>;
15751575
def : Pat<(lasxsplati64 GPR:$rj), (XVREPLGR2VR_D GPR:$rj)>;
15761576

1577+
def : Pat<(v32i8 (loongarch_vreplgr2vr GRLenVT:$rj)),
1578+
(v32i8 (XVREPLGR2VR_B GRLenVT:$rj))>;
1579+
def : Pat<(v16i16 (loongarch_vreplgr2vr GRLenVT:$rj)),
1580+
(v16i16 (XVREPLGR2VR_H GRLenVT:$rj))>;
1581+
def : Pat<(v8i32 (loongarch_vreplgr2vr GRLenVT:$rj)),
1582+
(v8i32 (XVREPLGR2VR_W GRLenVT:$rj))>;
1583+
def : Pat<(v4i64 (loongarch_vreplgr2vr GRLenVT:$rj)),
1584+
(v4i64 (XVREPLGR2VR_D GRLenVT:$rj))>;
1585+
15771586
// XVREPLVE_{B/H/W/D}
15781587
def : Pat<(loongarch_vreplve v32i8:$xj, GRLenVT:$rk),
15791588
(XVREPLVE_B v32i8:$xj, GRLenVT:$rk)>;

‎llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ def SDT_LoongArchV2R : SDTypeProfile<1, 2, [SDTCisVec<0>,
2323
SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
2424
def SDT_LoongArchV1RUimm: SDTypeProfile<1, 2, [SDTCisVec<0>,
2525
SDTCisSameAs<0,1>, SDTCisVT<2, i64>]>;
26+
def SDT_LoongArchVreplgr2vr : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>]>;
2627
def SDT_LoongArchVFRECIPE : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
2728
def SDT_LoongArchVFRSQRTE : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
2829

@@ -52,6 +53,8 @@ def loongarch_vilvh: SDNode<"LoongArchISD::VILVH", SDT_LoongArchV2R>;
5253

5354
def loongarch_vshuf4i: SDNode<"LoongArchISD::VSHUF4I", SDT_LoongArchV1RUimm>;
5455
def loongarch_vreplvei: SDNode<"LoongArchISD::VREPLVEI", SDT_LoongArchV1RUimm>;
56+
def loongarch_vreplgr2vr: SDNode<"LoongArchISD::VREPLGR2VR", SDT_LoongArchVreplgr2vr>;
57+
5558
def loongarch_vfrecipe: SDNode<"LoongArchISD::FRECIPE", SDT_LoongArchVFRECIPE>;
5659
def loongarch_vfrsqrte: SDNode<"LoongArchISD::FRSQRTE", SDT_LoongArchVFRSQRTE>;
5760

@@ -1737,6 +1740,15 @@ def : Pat<(lsxsplati16 GPR:$rj), (VREPLGR2VR_H GPR:$rj)>;
17371740
def : Pat<(lsxsplati32 GPR:$rj), (VREPLGR2VR_W GPR:$rj)>;
17381741
def : Pat<(lsxsplati64 GPR:$rj), (VREPLGR2VR_D GPR:$rj)>;
17391742

1743+
def : Pat<(v16i8 (loongarch_vreplgr2vr GRLenVT:$rj)),
1744+
(v16i8 (VREPLGR2VR_B GRLenVT:$rj))>;
1745+
def : Pat<(v8i16 (loongarch_vreplgr2vr GRLenVT:$rj)),
1746+
(v8i16 (VREPLGR2VR_H GRLenVT:$rj))>;
1747+
def : Pat<(v4i32 (loongarch_vreplgr2vr GRLenVT:$rj)),
1748+
(v4i32 (VREPLGR2VR_W GRLenVT:$rj))>;
1749+
def : Pat<(v2i64 (loongarch_vreplgr2vr GRLenVT:$rj)),
1750+
(v2i64 (VREPLGR2VR_D GRLenVT:$rj))>;
1751+
17401752
// VREPLVE_{B/H/W/D}
17411753
def : Pat<(loongarch_vreplve v16i8:$vj, GRLenVT:$rk),
17421754
(VREPLVE_B v16i8:$vj, GRLenVT:$rk)>;

‎llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl-ins-gr2vr.ll‎

Lines changed: 2 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4,14 +4,8 @@
44
define <8 x i32> @xvrepl_ins_w(i32 %a, i32 %b) {
55
; CHECK-LABEL: xvrepl_ins_w:
66
; CHECK: # %bb.0: # %entry
7-
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 0
7+
; CHECK-NEXT: xvreplgr2vr.w $xr0, $a0
88
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 1
9-
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 2
10-
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 3
11-
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 4
12-
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 5
13-
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 6
14-
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 7
159
; CHECK-NEXT: ret
1610
entry:
1711
%0 = call <8 x i32> @llvm.loongarch.lasx.xvreplgr2vr.w(i32 %a)
@@ -22,10 +16,8 @@ entry:
2216
define <4 x i64> @xvrepl_ins_d(i64 %a, i64 %b) {
2317
; CHECK-LABEL: xvrepl_ins_d:
2418
; CHECK: # %bb.0: # %entry
25-
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 0
19+
; CHECK-NEXT: xvreplgr2vr.d $xr0, $a0
2620
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 1
27-
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 2
28-
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 3
2921
; CHECK-NEXT: ret
3022
entry:
3123
%0 = call <4 x i64> @llvm.loongarch.lasx.xvreplgr2vr.d(i64 %a)

‎llvm/test/CodeGen/LoongArch/lsx/intrinsic-repl-ins-gr2vr.ll‎

Lines changed: 4 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -4,22 +4,8 @@
44
define <16 x i8> @vrepl_ins_b(i32 %a, i32 %b) {
55
; CHECK-LABEL: vrepl_ins_b:
66
; CHECK: # %bb.0: # %entry
7-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 0
7+
; CHECK-NEXT: vreplgr2vr.b $vr0, $a0
88
; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 1
9-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 2
10-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 3
11-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 4
12-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 5
13-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 6
14-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 7
15-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 8
16-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 9
17-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 10
18-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 11
19-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 12
20-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 13
21-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 14
22-
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 15
239
; CHECK-NEXT: ret
2410
entry:
2511
%0 = call <16 x i8> @llvm.loongarch.lsx.vreplgr2vr.b(i32 %a)
@@ -30,14 +16,8 @@ entry:
3016
define <8 x i16> @vrepl_ins_h(i32 %a, i32 %b) {
3117
; CHECK-LABEL: vrepl_ins_h:
3218
; CHECK: # %bb.0: # %entry
33-
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
19+
; CHECK-NEXT: vreplgr2vr.h $vr0, $a0
3420
; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 1
35-
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 2
36-
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 3
37-
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 4
38-
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 5
39-
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 6
40-
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 7
4121
; CHECK-NEXT: ret
4222
entry:
4323
%0 = call <8 x i16> @llvm.loongarch.lsx.vreplgr2vr.h(i32 %a)
@@ -48,10 +28,8 @@ entry:
4828
define <4 x i32> @vrepl_ins_w(i32 %a, i32 %b) {
4929
; CHECK-LABEL: vrepl_ins_w:
5030
; CHECK: # %bb.0: # %entry
51-
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
31+
; CHECK-NEXT: vreplgr2vr.w $vr0, $a0
5232
; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 1
53-
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 2
54-
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 3
5533
; CHECK-NEXT: ret
5634
entry:
5735
%0 = call <4 x i32> @llvm.loongarch.lsx.vreplgr2vr.w(i32 %a)
@@ -62,7 +40,7 @@ entry:
6240
define <2 x i64> @vrepl_ins_d(i64 %a, i64 %b) {
6341
; CHECK-LABEL: vrepl_ins_d:
6442
; CHECK: # %bb.0: # %entry
65-
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
43+
; CHECK-NEXT: vreplgr2vr.d $vr0, $a0
6644
; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 1
6745
; CHECK-NEXT: ret
6846
entry:

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