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andreisfrandreisfr
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[PATCH] [Xtensa] Remove redundant code.
1 parent 2b1a8b1 commit 51518b9

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7 files changed

+6
-255
lines changed

7 files changed

+6
-255
lines changed

‎llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -69,9 +69,6 @@ void XtensaAsmPrinter::emitMachineConstantPoolValue(
6969
const BlockAddress *BA =
7070
cast<XtensaConstantPoolConstant>(ACPV)->getBlockAddress();
7171
MCSym = GetBlockAddressSymbol(BA);
72-
} else if (ACPV->isMachineBasicBlock()) {
73-
const MachineBasicBlock *MBB = cast<XtensaConstantPoolMBB>(ACPV)->getMBB();
74-
MCSym = MBB->getSymbol();
7572
} else if (ACPV->isJumpTable()) {
7673
unsigned Idx = cast<XtensaConstantPoolJumpTable>(ACPV)->getIndex();
7774
MCSym = this->GetJTISymbol(Idx, false);

‎llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp‎

Lines changed: 0 additions & 180 deletions
Original file line numberDiff line numberDiff line change
@@ -13,13 +13,11 @@
1313
//===----------------------------------------------------------------------===//
1414

1515
#include "XtensaInstrInfo.h"
16-
#include "XtensaConstantPoolValue.h"
1716
#include "XtensaTargetMachine.h"
1817
#include "llvm/CodeGen/MachineConstantPool.h"
1918
#include "llvm/CodeGen/MachineFrameInfo.h"
2019
#include "llvm/CodeGen/MachineInstrBuilder.h"
2120
#include "llvm/CodeGen/MachineRegisterInfo.h"
22-
#include "llvm/CodeGen/RegisterScavenging.h"
2321

2422
#define GET_INSTRINFO_CTOR_DTOR
2523
#include "XtensaGenInstrInfo.inc"
@@ -188,18 +186,6 @@ void XtensaInstrInfo::loadImmediate(MachineBasicBlock &MBB,
188186
}
189187
}
190188

191-
unsigned XtensaInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
192-
switch (MI.getOpcode()) {
193-
case TargetOpcode::INLINEASM: { // Inline Asm: Variable size.
194-
const MachineFunction *MF = MI.getParent()->getParent();
195-
const char *AsmStr = MI.getOperand(0).getSymbolName();
196-
return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
197-
}
198-
default:
199-
return MI.getDesc().getSize();
200-
}
201-
}
202-
203189
bool XtensaInstrInfo::reverseBranchCondition(
204190
SmallVectorImpl<MachineOperand> &Cond) const {
205191
assert(Cond.size() <= 4 && "Invalid branch condition!");
@@ -261,77 +247,6 @@ bool XtensaInstrInfo::reverseBranchCondition(
261247
}
262248
}
263249

264-
MachineBasicBlock *
265-
XtensaInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
266-
unsigned OpCode = MI.getOpcode();
267-
switch (OpCode) {
268-
case Xtensa::BR_JT:
269-
case Xtensa::JX:
270-
return nullptr;
271-
case Xtensa::J:
272-
return MI.getOperand(0).getMBB();
273-
case Xtensa::BEQ:
274-
case Xtensa::BNE:
275-
case Xtensa::BLT:
276-
case Xtensa::BLTU:
277-
case Xtensa::BGE:
278-
case Xtensa::BGEU:
279-
return MI.getOperand(2).getMBB();
280-
281-
case Xtensa::BEQI:
282-
case Xtensa::BNEI:
283-
case Xtensa::BLTI:
284-
case Xtensa::BLTUI:
285-
case Xtensa::BGEI:
286-
case Xtensa::BGEUI:
287-
return MI.getOperand(2).getMBB();
288-
289-
case Xtensa::BEQZ:
290-
case Xtensa::BNEZ:
291-
case Xtensa::BLTZ:
292-
case Xtensa::BGEZ:
293-
return MI.getOperand(1).getMBB();
294-
295-
default:
296-
llvm_unreachable("Unknown branch opcode");
297-
}
298-
}
299-
300-
bool XtensaInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
301-
int64_t BrOffset) const {
302-
switch (BranchOp) {
303-
case Xtensa::J:
304-
BrOffset -= 4;
305-
return isIntN(18, BrOffset);
306-
case Xtensa::JX:
307-
return true;
308-
case Xtensa::BR_JT:
309-
return true;
310-
case Xtensa::BEQ:
311-
case Xtensa::BNE:
312-
case Xtensa::BLT:
313-
case Xtensa::BLTU:
314-
case Xtensa::BGE:
315-
case Xtensa::BGEU:
316-
case Xtensa::BEQI:
317-
case Xtensa::BNEI:
318-
case Xtensa::BLTI:
319-
case Xtensa::BLTUI:
320-
case Xtensa::BGEI:
321-
case Xtensa::BGEUI:
322-
BrOffset -= 4;
323-
return isIntN(8, BrOffset);
324-
case Xtensa::BEQZ:
325-
case Xtensa::BNEZ:
326-
case Xtensa::BLTZ:
327-
case Xtensa::BGEZ:
328-
BrOffset -= 4;
329-
return isIntN(12, BrOffset);
330-
default:
331-
llvm_unreachable("Unknown branch opcode");
332-
}
333-
}
334-
335250
bool XtensaInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
336251
MachineBasicBlock *&TBB,
337252
MachineBasicBlock *&FBB,
@@ -464,101 +379,6 @@ unsigned XtensaInstrInfo::insertBranch(
464379
return Count;
465380
}
466381

467-
void XtensaInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
468-
MachineBasicBlock &DestBB,
469-
MachineBasicBlock &RestoreBB,
470-
const DebugLoc &DL, int64_t BrOffset,
471-
RegScavenger *RS) const {
472-
assert(RS && "RegScavenger required for long branching");
473-
assert(MBB.empty() &&
474-
"new block should be inserted for expanding unconditional branch");
475-
assert(MBB.pred_size() == 1);
476-
477-
MachineFunction *MF = MBB.getParent();
478-
MachineRegisterInfo &MRI = MF->getRegInfo();
479-
MachineConstantPool *ConstantPool = MF->getConstantPool();
480-
481-
if (!isInt<32>(BrOffset))
482-
report_fatal_error(
483-
"Branch offsets outside of the signed 32-bit range not supported");
484-
XtensaConstantPoolValue *C =
485-
XtensaConstantPoolMBB::Create(MF->getFunction().getContext(), &DestBB, 0);
486-
unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align(4));
487-
488-
// FIXME: A virtual register must be used initially, as the register
489-
// scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
490-
// uses the same workaround).
491-
Register ScratchReg = MRI.createVirtualRegister(&Xtensa::ARRegClass);
492-
auto II = MBB.end();
493-
494-
MachineInstr &L32R = *BuildMI(MBB, II, DL, get(Xtensa::L32R), ScratchReg)
495-
.addConstantPoolIndex(Idx);
496-
BuildMI(MBB, II, DL, get(Xtensa::JX)).addReg(ScratchReg, RegState::Kill);
497-
RS->enterBasicBlockEnd(MBB);
498-
unsigned Scav = RS->scavengeRegisterBackwards(Xtensa::ARRegClass,
499-
L32R.getIterator(), false, 0);
500-
MRI.replaceRegWith(ScratchReg, Scav);
501-
MRI.clearVirtRegs();
502-
RS->setRegUsed(Scav);
503-
}
504-
505-
unsigned XtensaInstrInfo::InsertConstBranchAtInst(
506-
MachineBasicBlock &MBB, MachineInstr *I, int64_t offset,
507-
ArrayRef<MachineOperand> Cond, DebugLoc DL, int *BytesAdded) const {
508-
// Shouldn't be a fall through.
509-
assert(&MBB && "InsertBranch must not be told to insert a fallthrough");
510-
assert(Cond.size() <= 4 &&
511-
"Xtensa branch conditions have less than four components!");
512-
513-
if (Cond.empty() || (Cond[0].getImm() == Xtensa::J)) {
514-
// Unconditional branch
515-
MachineInstr *MI = BuildMI(MBB, I, DL, get(Xtensa::J)).addImm(offset);
516-
if (BytesAdded && MI)
517-
*BytesAdded += getInstSizeInBytes(*MI);
518-
return 1;
519-
}
520-
521-
unsigned Count = 0;
522-
unsigned BR_C = Cond[0].getImm();
523-
MachineInstr *MI = nullptr;
524-
switch (BR_C) {
525-
case Xtensa::BEQ:
526-
case Xtensa::BNE:
527-
case Xtensa::BLT:
528-
case Xtensa::BLTU:
529-
case Xtensa::BGE:
530-
case Xtensa::BGEU:
531-
MI = BuildMI(MBB, I, DL, get(BR_C))
532-
.addImm(offset)
533-
.addReg(Cond[1].getReg())
534-
.addReg(Cond[2].getReg());
535-
break;
536-
case Xtensa::BEQI:
537-
case Xtensa::BNEI:
538-
case Xtensa::BLTI:
539-
case Xtensa::BLTUI:
540-
case Xtensa::BGEI:
541-
case Xtensa::BGEUI:
542-
MI = BuildMI(MBB, I, DL, get(BR_C))
543-
.addImm(offset)
544-
.addReg(Cond[1].getReg())
545-
.addImm(Cond[2].getImm());
546-
break;
547-
case Xtensa::BEQZ:
548-
case Xtensa::BNEZ:
549-
case Xtensa::BLTZ:
550-
case Xtensa::BGEZ:
551-
MI = BuildMI(MBB, I, DL, get(BR_C)).addImm(offset).addReg(Cond[1].getReg());
552-
break;
553-
default:
554-
llvm_unreachable("Invalid branch type!");
555-
}
556-
if (BytesAdded && MI)
557-
*BytesAdded += getInstSizeInBytes(*MI);
558-
++Count;
559-
return Count;
560-
}
561-
562382
unsigned XtensaInstrInfo::InsertBranchAtInst(MachineBasicBlock &MBB,
563383
MachineBasicBlock::iterator I,
564384
MachineBasicBlock *TBB,

‎llvm/lib/Target/Xtensa/XtensaInstrInfo.h‎

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,6 @@ class XtensaInstrInfo : public XtensaGenInstrInfo {
3838
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
3939
MachineBasicBlock::iterator I) const;
4040

41-
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
42-
4341
// Return the XtensaRegisterInfo, which this class owns.
4442
const XtensaRegisterInfo &getRegisterInfo() const { return RI; }
4543

@@ -79,11 +77,6 @@ class XtensaInstrInfo : public XtensaGenInstrInfo {
7977
bool
8078
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
8179

82-
MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
83-
84-
bool isBranchOffsetInRange(unsigned BranchOpc,
85-
int64_t BrOffset) const override;
86-
8780
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
8881
MachineBasicBlock *&FBB,
8982
SmallVectorImpl<MachineOperand> &Cond,
@@ -97,22 +90,12 @@ class XtensaInstrInfo : public XtensaGenInstrInfo {
9790
const DebugLoc &DL,
9891
int *BytesAdded = nullptr) const override;
9992

100-
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &DestBB,
101-
MachineBasicBlock &RestoreBB, const DebugLoc &DL,
102-
int64_t BrOffset = 0,
103-
RegScavenger *RS = nullptr) const override;
104-
10593
unsigned InsertBranchAtInst(MachineBasicBlock &MBB,
10694
MachineBasicBlock::iterator I,
10795
MachineBasicBlock *TBB,
10896
ArrayRef<MachineOperand> Cond, const DebugLoc &DL,
10997
int *BytesAdded) const;
11098

111-
unsigned InsertConstBranchAtInst(MachineBasicBlock &MBB, MachineInstr *I,
112-
int64_t offset,
113-
ArrayRef<MachineOperand> Cond, DebugLoc DL,
114-
int *BytesAdded) const;
115-
11699
// Return true if MI is a conditional or unconditional branch.
117100
// When returning true, set Cond to the mask of condition-code
118101
// values on which the instruction will branch, and set Target

‎llvm/lib/Target/Xtensa/XtensaRegisterInfo.h‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -38,10 +38,6 @@ class XtensaRegisterInfo : public XtensaGenRegisterInfo {
3838
return true;
3939
}
4040

41-
bool trackLivenessAfterRegAlloc(const MachineFunction &) const override {
42-
return true;
43-
}
44-
4541
const uint16_t *
4642
getCalleeSavedRegs(const MachineFunction *MF = 0) const override;
4743
const uint32_t *getCallPreservedMask(const MachineFunction &MF,

‎llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,6 @@ class XtensaPassConfig : public TargetPassConfig {
9595
}
9696

9797
bool addInstSelector() override;
98-
void addPreEmitPass() override;
9998
};
10099
} // end anonymous namespace
101100

@@ -104,8 +103,6 @@ bool XtensaPassConfig::addInstSelector() {
104103
return false;
105104
}
106105

107-
void XtensaPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
108-
109106
TargetPassConfig *XtensaTargetMachine::createPassConfig(PassManagerBase &PM) {
110107
return new XtensaPassConfig(*this, PM);
111108
}

‎llvm/test/CodeGen/Xtensa/branch-relaxation.ll‎

Lines changed: 0 additions & 42 deletions
This file was deleted.

‎llvm/test/CodeGen/Xtensa/ctlz-cttz-ctpop.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@ declare i32 @llvm.ctpop.i32(i32)
88

99
define i32 @test_cttz_i32(i32 %a) nounwind {
1010
; XTENSA-LABEL: test_cttz_i32:
11-
; XTENSA: beqz a2, .LBB0_2
12-
; XTENSA-NEXT: # %bb.1: # %cond.false
11+
; XTENSA: beqz a2, .LBB0_1
12+
; XTENSA-NEXT: # %bb.2: # %cond.false
1313
; XTENSA-NEXT: movi a8, -1
1414
; XTENSA-NEXT: xor a8, a2, a8
1515
; XTENSA-NEXT: addi a9, a2, -1
@@ -33,7 +33,7 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
3333
; XTENSA-NEXT: add a8, a8, a9
3434
; XTENSA-NEXT: extui a2, a8, 24, 8
3535
; XTENSA-NEXT: ret
36-
; XTENSA-NEXT: .LBB0_2:
36+
; XTENSA-NEXT: .LBB0_1:
3737
; XTENSA-NEXT: movi a2, 32
3838
; XTENSA-NEXT: ret
3939
%tmp = call i32 @llvm.cttz.i32(i32 %a, i1 false)
@@ -71,8 +71,8 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
7171

7272
define i32 @test_ctlz_i32(i32 %a) nounwind {
7373
; XTENSA-LABEL: test_ctlz_i32:
74-
; XTENSA: beqz a2, .LBB2_2
75-
; XTENSA-NEXT: # %bb.1: # %cond.false
74+
; XTENSA: beqz a2, .LBB2_1
75+
; XTENSA-NEXT: # %bb.2: # %cond.false
7676
; XTENSA-NEXT: srli a8, a2, 1
7777
; XTENSA-NEXT: or a8, a2, a8
7878
; XTENSA-NEXT: srli a9, a8, 2
@@ -104,7 +104,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
104104
; XTENSA-NEXT: add a8, a8, a9
105105
; XTENSA-NEXT: extui a2, a8, 24, 8
106106
; XTENSA-NEXT: ret
107-
; XTENSA-NEXT: .LBB2_2:
107+
; XTENSA-NEXT: .LBB2_1:
108108
; XTENSA-NEXT: movi a2, 32
109109
; XTENSA-NEXT: ret
110110
%tmp = call i32 @llvm.ctlz.i32(i32 %a, i1 false)

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