- Address reviewer comments

Author: perlfu

llvm/docs/AMDGPUUsage.rst

@@ -1717,7 +1717,7 @@ The AMDGPU backend supports the following LLVM IR attributes.
 
      "amdgpu-sgpr-hazard-mem-wait-cull"      Enable insertion of SGPR hazard cull sequences before memory waits.
                                              Cull sequence reduces future hazard waits, but has a performance cost.
-                                             Attempt to amortize cost by overlaping with memory access.
+                                             Attempt to amortize cost by overlapping with memory accesses.
 
      "amdgpu-sgpr-hazard-mem-wait-cull-threshold"
                                              Sets the number of active SGPR hazards that must be present before

llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir

@@ -1,25 +1,25 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -run-pass post-RA-hazard-rec,amdgpu-wait-sgpr-hazards -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass post-RA-hazard-rec,amdgpu-wait-sgpr-hazards -o - %s | FileCheck -check-prefix=GCN %s
 
 --- |
-  @mem = internal unnamed_addr addrspace(4) constant [4 x <4 x i32>] [<4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>]
-
   define amdgpu_gs void @hazard_disable() #0 { ret void }
-  define amdgpu_cs void @hazard_calls() #1 { ret void }
-  define void @hazard_callee1() #1 { ret void }
-  define void @hazard_callee2() #1 { ret void }
-  define amdgpu_cs void @hazard_cull_vmem() #2 { ret void }
-  define amdgpu_cs void @hazard_cull_vmem2() #3 { ret void }
-  define amdgpu_cs void @hazard_cull_sample() #2 { ret void }
-  define amdgpu_cs void @hazard_cull_bvh() #2 { ret void }
-  define amdgpu_cs void @hazard_nocull_scratch() #2 { ret void }
-  define amdgpu_cs void @hazard_cull_global() #2 { ret void }
-  define amdgpu_cs void @hazard_nocull_flat() #2 { ret void }
+  define amdgpu_gs void @hazard_enable() #1 { ret void }
+  define amdgpu_cs void @hazard_calls() #2 { ret void }
+  define void @hazard_callee1() #2 { ret void }
+  define void @hazard_callee2() #2 { ret void }
+  define amdgpu_cs void @hazard_cull_vmem() #3 { ret void }
+  define amdgpu_cs void @hazard_cull_vmem2() #4 { ret void }
+  define amdgpu_cs void @hazard_cull_sample() #3 { ret void }
+  define amdgpu_cs void @hazard_cull_bvh() #3 { ret void }
+  define amdgpu_cs void @hazard_nocull_scratch() #3 { ret void }
+  define amdgpu_cs void @hazard_cull_global() #3 { ret void }
+  define amdgpu_cs void @hazard_nocull_flat() #3 { ret void }
 
   attributes #0 = { "amdgpu-sgpr-hazard-wait"="0" }
-  attributes #1 = { "amdgpu-sgpr-hazard-boundary-cull" }
-  attributes #2 = { "amdgpu-sgpr-hazard-mem-wait-cull" "amdgpu-sgpr-hazard-mem-wait-cull-threshold"="1" }
-  attributes #3 = { "amdgpu-sgpr-hazard-mem-wait-cull" "amdgpu-sgpr-hazard-mem-wait-cull-threshold"="2" }
+  attributes #1 = { "amdgpu-sgpr-hazard-wait"="1" }
+  attributes #2 = { "amdgpu-sgpr-hazard-boundary-cull" }
+  attributes #3 = { "amdgpu-sgpr-hazard-mem-wait-cull" "amdgpu-sgpr-hazard-mem-wait-cull-threshold"="1" }
+  attributes #4 = { "amdgpu-sgpr-hazard-mem-wait-cull" "amdgpu-sgpr-hazard-mem-wait-cull-threshold"="2" }
 ...
 
 ---
@@ -37,6 +37,22 @@ body:            |
     S_ENDPGM 0
 ...
 
+---
+name:            hazard_enable
+body:            |
+  bb.0:
+    ; GCN-LABEL: name: hazard_enable
+    ; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0, implicit $exec
+    ; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
+    ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+    ; GCN-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
+    ; GCN-NEXT: S_ENDPGM 0
+    $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0, implicit $exec
+    $sgpr0_sgpr1 = S_GETPC_B64
+    $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
+    S_ENDPGM 0
+...
+
 ---
 name:            hazard_calls
 frameInfo: