Skip to content

Commit 5184912

Browse files
RKSimonRKSimon
committed
[DAG] Fold build_vector(build_pair()) patterns.
If an integer build_vector node purely contains build_pair nodes, then attempt to remove the build_pair and create a build_vector with the internal elements directly. For build_vector(build_pair(x,y)) the patch folds to bitcast(build_pair(x,y)) directly. This helps fix a lot of MMX codegen (yay.....), but also avoids a number of regressions. I'm not sure what to do with the RISCV regressions (or whether they are all regressions), I was able to reduce some by not creating RISCVISD::VSLIDE1DOWN_VL nodes when inserting UNDEF elements, but I need some hints on what else to try.
1 parent dbf44c2 commit 5184912

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

41 files changed

+3680
-5207
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25203,6 +25203,29 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
2520325203
return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, V);
2520425204
}
2520525205

25206+
// build_vector(build_pair(x,y)) -> bitcast(build_pair(x,y))
25207+
if (N->getNumOperands() == 1 &&
25208+
N->getOperand(0).getOpcode() == ISD::BUILD_PAIR)
25209+
return DAG.getBitcast(VT, N->getOperand(0));
25210+
25211+
// build_vector(build_pair(x,y),build_pair(z,w),...)
25212+
// --> bitcast(build_vector(x,y,z,w,...))
25213+
if (VT.isInteger() && !cast<BuildVectorSDNode>(N)->getSplatValue() &&
25214+
all_of(N->ops(),
25215+
[](SDValue Op) { return Op.getOpcode() == ISD::BUILD_PAIR; })) {
25216+
EVT PairSVT = N->getOperand(0).getOperand(0).getValueType();
25217+
EVT PairVT = EVT::getVectorVT(*DAG.getContext(), PairSVT,
25218+
VT.getVectorElementCount() * 2);
25219+
unsigned Lo = DAG.getDataLayout().isBigEndian() ? 1 : 0;
25220+
unsigned Hi = 1 - Lo;
25221+
SmallVector<SDValue, 4> PairOps;
25222+
for (SDValue Op : N->ops()) {
25223+
PairOps.push_back(Op.getOperand(Lo));
25224+
PairOps.push_back(Op.getOperand(Hi));
25225+
}
25226+
return DAG.getBitcast(VT, DAG.getBuildVector(PairVT, SDLoc(N), PairOps));
25227+
}
25228+
2520625229
return SDValue();
2520725230
}
2520825231

‎llvm/test/CodeGen/AArch64/andorxor.ll‎

Lines changed: 207 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -1319,10 +1319,20 @@ entry:
13191319
define <2 x i128> @and_v2i128(<2 x i128> %d, <2 x i128> %e) {
13201320
; CHECK-SD-LABEL: and_v2i128:
13211321
; CHECK-SD: // %bb.0: // %entry
1322-
; CHECK-SD-NEXT: and x2, x2, x6
1323-
; CHECK-SD-NEXT: and x0, x0, x4
1324-
; CHECK-SD-NEXT: and x1, x1, x5
1325-
; CHECK-SD-NEXT: and x3, x3, x7
1322+
; CHECK-SD-NEXT: fmov d0, x4
1323+
; CHECK-SD-NEXT: fmov d1, x0
1324+
; CHECK-SD-NEXT: fmov d2, x6
1325+
; CHECK-SD-NEXT: fmov d3, x2
1326+
; CHECK-SD-NEXT: mov v0.d[1], x5
1327+
; CHECK-SD-NEXT: mov v1.d[1], x1
1328+
; CHECK-SD-NEXT: mov v2.d[1], x7
1329+
; CHECK-SD-NEXT: mov v3.d[1], x3
1330+
; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b
1331+
; CHECK-SD-NEXT: and v2.16b, v3.16b, v2.16b
1332+
; CHECK-SD-NEXT: mov x1, v0.d[1]
1333+
; CHECK-SD-NEXT: fmov x0, d0
1334+
; CHECK-SD-NEXT: mov x3, v2.d[1]
1335+
; CHECK-SD-NEXT: fmov x2, d2
13261336
; CHECK-SD-NEXT: ret
13271337
;
13281338
; CHECK-GI-LABEL: and_v2i128:
@@ -1340,10 +1350,20 @@ entry:
13401350
define <2 x i128> @or_v2i128(<2 x i128> %d, <2 x i128> %e) {
13411351
; CHECK-SD-LABEL: or_v2i128:
13421352
; CHECK-SD: // %bb.0: // %entry
1343-
; CHECK-SD-NEXT: orr x2, x2, x6
1344-
; CHECK-SD-NEXT: orr x0, x0, x4
1345-
; CHECK-SD-NEXT: orr x1, x1, x5
1346-
; CHECK-SD-NEXT: orr x3, x3, x7
1353+
; CHECK-SD-NEXT: fmov d0, x4
1354+
; CHECK-SD-NEXT: fmov d1, x0
1355+
; CHECK-SD-NEXT: fmov d2, x6
1356+
; CHECK-SD-NEXT: fmov d3, x2
1357+
; CHECK-SD-NEXT: mov v0.d[1], x5
1358+
; CHECK-SD-NEXT: mov v1.d[1], x1
1359+
; CHECK-SD-NEXT: mov v2.d[1], x7
1360+
; CHECK-SD-NEXT: mov v3.d[1], x3
1361+
; CHECK-SD-NEXT: orr v0.16b, v1.16b, v0.16b
1362+
; CHECK-SD-NEXT: orr v2.16b, v3.16b, v2.16b
1363+
; CHECK-SD-NEXT: mov x1, v0.d[1]
1364+
; CHECK-SD-NEXT: fmov x0, d0
1365+
; CHECK-SD-NEXT: mov x3, v2.d[1]
1366+
; CHECK-SD-NEXT: fmov x2, d2
13471367
; CHECK-SD-NEXT: ret
13481368
;
13491369
; CHECK-GI-LABEL: or_v2i128:
@@ -1361,10 +1381,20 @@ entry:
13611381
define <2 x i128> @xor_v2i128(<2 x i128> %d, <2 x i128> %e) {
13621382
; CHECK-SD-LABEL: xor_v2i128:
13631383
; CHECK-SD: // %bb.0: // %entry
1364-
; CHECK-SD-NEXT: eor x2, x2, x6
1365-
; CHECK-SD-NEXT: eor x0, x0, x4
1366-
; CHECK-SD-NEXT: eor x1, x1, x5
1367-
; CHECK-SD-NEXT: eor x3, x3, x7
1384+
; CHECK-SD-NEXT: fmov d0, x4
1385+
; CHECK-SD-NEXT: fmov d1, x0
1386+
; CHECK-SD-NEXT: fmov d2, x6
1387+
; CHECK-SD-NEXT: fmov d3, x2
1388+
; CHECK-SD-NEXT: mov v0.d[1], x5
1389+
; CHECK-SD-NEXT: mov v1.d[1], x1
1390+
; CHECK-SD-NEXT: mov v2.d[1], x7
1391+
; CHECK-SD-NEXT: mov v3.d[1], x3
1392+
; CHECK-SD-NEXT: eor v0.16b, v1.16b, v0.16b
1393+
; CHECK-SD-NEXT: eor v2.16b, v3.16b, v2.16b
1394+
; CHECK-SD-NEXT: mov x1, v0.d[1]
1395+
; CHECK-SD-NEXT: fmov x0, d0
1396+
; CHECK-SD-NEXT: mov x3, v2.d[1]
1397+
; CHECK-SD-NEXT: fmov x2, d2
13681398
; CHECK-SD-NEXT: ret
13691399
;
13701400
; CHECK-GI-LABEL: xor_v2i128:
@@ -1382,14 +1412,29 @@ entry:
13821412
define <3 x i128> @and_v3i128(<3 x i128> %d, <3 x i128> %e) {
13831413
; CHECK-SD-LABEL: and_v3i128:
13841414
; CHECK-SD: // %bb.0: // %entry
1385-
; CHECK-SD-NEXT: ldp x8, x9, [sp]
1386-
; CHECK-SD-NEXT: and x0, x0, x6
1387-
; CHECK-SD-NEXT: ldp x11, x10, [sp, #16]
1388-
; CHECK-SD-NEXT: and x1, x1, x7
1389-
; CHECK-SD-NEXT: and x2, x2, x8
1390-
; CHECK-SD-NEXT: and x3, x3, x9
1391-
; CHECK-SD-NEXT: and x4, x4, x11
1392-
; CHECK-SD-NEXT: and x5, x5, x10
1415+
; CHECK-SD-NEXT: fmov d0, x6
1416+
; CHECK-SD-NEXT: fmov d1, x0
1417+
; CHECK-SD-NEXT: ldr d2, [sp]
1418+
; CHECK-SD-NEXT: fmov d3, x2
1419+
; CHECK-SD-NEXT: fmov d5, x4
1420+
; CHECK-SD-NEXT: ldr d4, [sp, #16]
1421+
; CHECK-SD-NEXT: add x8, sp, #8
1422+
; CHECK-SD-NEXT: add x9, sp, #24
1423+
; CHECK-SD-NEXT: mov v0.d[1], x7
1424+
; CHECK-SD-NEXT: mov v1.d[1], x1
1425+
; CHECK-SD-NEXT: ld1 { v2.d }[1], [x8]
1426+
; CHECK-SD-NEXT: mov v3.d[1], x3
1427+
; CHECK-SD-NEXT: mov v5.d[1], x5
1428+
; CHECK-SD-NEXT: ld1 { v4.d }[1], [x9]
1429+
; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b
1430+
; CHECK-SD-NEXT: and v1.16b, v5.16b, v4.16b
1431+
; CHECK-SD-NEXT: and v2.16b, v3.16b, v2.16b
1432+
; CHECK-SD-NEXT: mov x1, v0.d[1]
1433+
; CHECK-SD-NEXT: fmov x0, d0
1434+
; CHECK-SD-NEXT: mov x3, v2.d[1]
1435+
; CHECK-SD-NEXT: mov x5, v1.d[1]
1436+
; CHECK-SD-NEXT: fmov x2, d2
1437+
; CHECK-SD-NEXT: fmov x4, d1
13931438
; CHECK-SD-NEXT: ret
13941439
;
13951440
; CHECK-GI-LABEL: and_v3i128:
@@ -1411,14 +1456,29 @@ entry:
14111456
define <3 x i128> @or_v3i128(<3 x i128> %d, <3 x i128> %e) {
14121457
; CHECK-SD-LABEL: or_v3i128:
14131458
; CHECK-SD: // %bb.0: // %entry
1414-
; CHECK-SD-NEXT: ldp x8, x9, [sp]
1415-
; CHECK-SD-NEXT: orr x0, x0, x6
1416-
; CHECK-SD-NEXT: ldp x11, x10, [sp, #16]
1417-
; CHECK-SD-NEXT: orr x1, x1, x7
1418-
; CHECK-SD-NEXT: orr x2, x2, x8
1419-
; CHECK-SD-NEXT: orr x3, x3, x9
1420-
; CHECK-SD-NEXT: orr x4, x4, x11
1421-
; CHECK-SD-NEXT: orr x5, x5, x10
1459+
; CHECK-SD-NEXT: fmov d0, x6
1460+
; CHECK-SD-NEXT: fmov d1, x0
1461+
; CHECK-SD-NEXT: ldr d2, [sp]
1462+
; CHECK-SD-NEXT: fmov d3, x2
1463+
; CHECK-SD-NEXT: fmov d5, x4
1464+
; CHECK-SD-NEXT: ldr d4, [sp, #16]
1465+
; CHECK-SD-NEXT: add x8, sp, #8
1466+
; CHECK-SD-NEXT: add x9, sp, #24
1467+
; CHECK-SD-NEXT: mov v0.d[1], x7
1468+
; CHECK-SD-NEXT: mov v1.d[1], x1
1469+
; CHECK-SD-NEXT: ld1 { v2.d }[1], [x8]
1470+
; CHECK-SD-NEXT: mov v3.d[1], x3
1471+
; CHECK-SD-NEXT: mov v5.d[1], x5
1472+
; CHECK-SD-NEXT: ld1 { v4.d }[1], [x9]
1473+
; CHECK-SD-NEXT: orr v0.16b, v1.16b, v0.16b
1474+
; CHECK-SD-NEXT: orr v1.16b, v5.16b, v4.16b
1475+
; CHECK-SD-NEXT: orr v2.16b, v3.16b, v2.16b
1476+
; CHECK-SD-NEXT: mov x1, v0.d[1]
1477+
; CHECK-SD-NEXT: fmov x0, d0
1478+
; CHECK-SD-NEXT: mov x3, v2.d[1]
1479+
; CHECK-SD-NEXT: mov x5, v1.d[1]
1480+
; CHECK-SD-NEXT: fmov x2, d2
1481+
; CHECK-SD-NEXT: fmov x4, d1
14221482
; CHECK-SD-NEXT: ret
14231483
;
14241484
; CHECK-GI-LABEL: or_v3i128:
@@ -1440,14 +1500,29 @@ entry:
14401500
define <3 x i128> @xor_v3i128(<3 x i128> %d, <3 x i128> %e) {
14411501
; CHECK-SD-LABEL: xor_v3i128:
14421502
; CHECK-SD: // %bb.0: // %entry
1443-
; CHECK-SD-NEXT: ldp x8, x9, [sp]
1444-
; CHECK-SD-NEXT: eor x0, x0, x6
1445-
; CHECK-SD-NEXT: ldp x11, x10, [sp, #16]
1446-
; CHECK-SD-NEXT: eor x1, x1, x7
1447-
; CHECK-SD-NEXT: eor x2, x2, x8
1448-
; CHECK-SD-NEXT: eor x3, x3, x9
1449-
; CHECK-SD-NEXT: eor x4, x4, x11
1450-
; CHECK-SD-NEXT: eor x5, x5, x10
1503+
; CHECK-SD-NEXT: fmov d0, x6
1504+
; CHECK-SD-NEXT: fmov d1, x0
1505+
; CHECK-SD-NEXT: ldr d2, [sp]
1506+
; CHECK-SD-NEXT: fmov d3, x2
1507+
; CHECK-SD-NEXT: fmov d5, x4
1508+
; CHECK-SD-NEXT: ldr d4, [sp, #16]
1509+
; CHECK-SD-NEXT: add x8, sp, #8
1510+
; CHECK-SD-NEXT: add x9, sp, #24
1511+
; CHECK-SD-NEXT: mov v0.d[1], x7
1512+
; CHECK-SD-NEXT: mov v1.d[1], x1
1513+
; CHECK-SD-NEXT: ld1 { v2.d }[1], [x8]
1514+
; CHECK-SD-NEXT: mov v3.d[1], x3
1515+
; CHECK-SD-NEXT: mov v5.d[1], x5
1516+
; CHECK-SD-NEXT: ld1 { v4.d }[1], [x9]
1517+
; CHECK-SD-NEXT: eor v0.16b, v1.16b, v0.16b
1518+
; CHECK-SD-NEXT: eor v1.16b, v5.16b, v4.16b
1519+
; CHECK-SD-NEXT: eor v2.16b, v3.16b, v2.16b
1520+
; CHECK-SD-NEXT: mov x1, v0.d[1]
1521+
; CHECK-SD-NEXT: fmov x0, d0
1522+
; CHECK-SD-NEXT: mov x3, v2.d[1]
1523+
; CHECK-SD-NEXT: mov x5, v1.d[1]
1524+
; CHECK-SD-NEXT: fmov x2, d2
1525+
; CHECK-SD-NEXT: fmov x4, d1
14511526
; CHECK-SD-NEXT: ret
14521527
;
14531528
; CHECK-GI-LABEL: xor_v3i128:
@@ -1469,18 +1544,38 @@ entry:
14691544
define <4 x i128> @and_v4i128(<4 x i128> %d, <4 x i128> %e) {
14701545
; CHECK-SD-LABEL: and_v4i128:
14711546
; CHECK-SD: // %bb.0: // %entry
1472-
; CHECK-SD-NEXT: ldp x9, x8, [sp, #32]
1473-
; CHECK-SD-NEXT: ldp x11, x10, [sp]
1474-
; CHECK-SD-NEXT: ldp x13, x12, [sp, #16]
1475-
; CHECK-SD-NEXT: ldp x15, x14, [sp, #48]
1476-
; CHECK-SD-NEXT: and x4, x4, x9
1477-
; CHECK-SD-NEXT: and x0, x0, x11
1478-
; CHECK-SD-NEXT: and x1, x1, x10
1479-
; CHECK-SD-NEXT: and x5, x5, x8
1480-
; CHECK-SD-NEXT: and x2, x2, x13
1481-
; CHECK-SD-NEXT: and x3, x3, x12
1482-
; CHECK-SD-NEXT: and x6, x6, x15
1483-
; CHECK-SD-NEXT: and x7, x7, x14
1547+
; CHECK-SD-NEXT: ldr d0, [sp]
1548+
; CHECK-SD-NEXT: fmov d2, x0
1549+
; CHECK-SD-NEXT: fmov d3, x2
1550+
; CHECK-SD-NEXT: fmov d5, x4
1551+
; CHECK-SD-NEXT: fmov d7, x6
1552+
; CHECK-SD-NEXT: add x8, sp, #8
1553+
; CHECK-SD-NEXT: ldr d1, [sp, #16]
1554+
; CHECK-SD-NEXT: ld1 { v0.d }[1], [x8]
1555+
; CHECK-SD-NEXT: add x8, sp, #24
1556+
; CHECK-SD-NEXT: ldr d4, [sp, #32]
1557+
; CHECK-SD-NEXT: ldr d6, [sp, #48]
1558+
; CHECK-SD-NEXT: mov v2.d[1], x1
1559+
; CHECK-SD-NEXT: ld1 { v1.d }[1], [x8]
1560+
; CHECK-SD-NEXT: mov v3.d[1], x3
1561+
; CHECK-SD-NEXT: add x8, sp, #40
1562+
; CHECK-SD-NEXT: mov v5.d[1], x5
1563+
; CHECK-SD-NEXT: add x9, sp, #56
1564+
; CHECK-SD-NEXT: mov v7.d[1], x7
1565+
; CHECK-SD-NEXT: ld1 { v4.d }[1], [x8]
1566+
; CHECK-SD-NEXT: ld1 { v6.d }[1], [x9]
1567+
; CHECK-SD-NEXT: and v0.16b, v2.16b, v0.16b
1568+
; CHECK-SD-NEXT: and v1.16b, v3.16b, v1.16b
1569+
; CHECK-SD-NEXT: and v2.16b, v7.16b, v6.16b
1570+
; CHECK-SD-NEXT: and v3.16b, v5.16b, v4.16b
1571+
; CHECK-SD-NEXT: mov x1, v0.d[1]
1572+
; CHECK-SD-NEXT: fmov x0, d0
1573+
; CHECK-SD-NEXT: mov x3, v1.d[1]
1574+
; CHECK-SD-NEXT: fmov x2, d1
1575+
; CHECK-SD-NEXT: mov x5, v3.d[1]
1576+
; CHECK-SD-NEXT: mov x7, v2.d[1]
1577+
; CHECK-SD-NEXT: fmov x4, d3
1578+
; CHECK-SD-NEXT: fmov x6, d2
14841579
; CHECK-SD-NEXT: ret
14851580
;
14861581
; CHECK-GI-LABEL: and_v4i128:
@@ -1506,18 +1601,38 @@ entry:
15061601
define <4 x i128> @or_v4i128(<4 x i128> %d, <4 x i128> %e) {
15071602
; CHECK-SD-LABEL: or_v4i128:
15081603
; CHECK-SD: // %bb.0: // %entry
1509-
; CHECK-SD-NEXT: ldp x9, x8, [sp, #32]
1510-
; CHECK-SD-NEXT: ldp x11, x10, [sp]
1511-
; CHECK-SD-NEXT: ldp x13, x12, [sp, #16]
1512-
; CHECK-SD-NEXT: ldp x15, x14, [sp, #48]
1513-
; CHECK-SD-NEXT: orr x4, x4, x9
1514-
; CHECK-SD-NEXT: orr x0, x0, x11
1515-
; CHECK-SD-NEXT: orr x1, x1, x10
1516-
; CHECK-SD-NEXT: orr x5, x5, x8
1517-
; CHECK-SD-NEXT: orr x2, x2, x13
1518-
; CHECK-SD-NEXT: orr x3, x3, x12
1519-
; CHECK-SD-NEXT: orr x6, x6, x15
1520-
; CHECK-SD-NEXT: orr x7, x7, x14
1604+
; CHECK-SD-NEXT: ldr d0, [sp]
1605+
; CHECK-SD-NEXT: fmov d2, x0
1606+
; CHECK-SD-NEXT: fmov d3, x2
1607+
; CHECK-SD-NEXT: fmov d5, x4
1608+
; CHECK-SD-NEXT: fmov d7, x6
1609+
; CHECK-SD-NEXT: add x8, sp, #8
1610+
; CHECK-SD-NEXT: ldr d1, [sp, #16]
1611+
; CHECK-SD-NEXT: ld1 { v0.d }[1], [x8]
1612+
; CHECK-SD-NEXT: add x8, sp, #24
1613+
; CHECK-SD-NEXT: ldr d4, [sp, #32]
1614+
; CHECK-SD-NEXT: ldr d6, [sp, #48]
1615+
; CHECK-SD-NEXT: mov v2.d[1], x1
1616+
; CHECK-SD-NEXT: ld1 { v1.d }[1], [x8]
1617+
; CHECK-SD-NEXT: mov v3.d[1], x3
1618+
; CHECK-SD-NEXT: add x8, sp, #40
1619+
; CHECK-SD-NEXT: mov v5.d[1], x5
1620+
; CHECK-SD-NEXT: add x9, sp, #56
1621+
; CHECK-SD-NEXT: mov v7.d[1], x7
1622+
; CHECK-SD-NEXT: ld1 { v4.d }[1], [x8]
1623+
; CHECK-SD-NEXT: ld1 { v6.d }[1], [x9]
1624+
; CHECK-SD-NEXT: orr v0.16b, v2.16b, v0.16b
1625+
; CHECK-SD-NEXT: orr v1.16b, v3.16b, v1.16b
1626+
; CHECK-SD-NEXT: orr v2.16b, v7.16b, v6.16b
1627+
; CHECK-SD-NEXT: orr v3.16b, v5.16b, v4.16b
1628+
; CHECK-SD-NEXT: mov x1, v0.d[1]
1629+
; CHECK-SD-NEXT: fmov x0, d0
1630+
; CHECK-SD-NEXT: mov x3, v1.d[1]
1631+
; CHECK-SD-NEXT: fmov x2, d1
1632+
; CHECK-SD-NEXT: mov x5, v3.d[1]
1633+
; CHECK-SD-NEXT: mov x7, v2.d[1]
1634+
; CHECK-SD-NEXT: fmov x4, d3
1635+
; CHECK-SD-NEXT: fmov x6, d2
15211636
; CHECK-SD-NEXT: ret
15221637
;
15231638
; CHECK-GI-LABEL: or_v4i128:
@@ -1543,18 +1658,38 @@ entry:
15431658
define <4 x i128> @xor_v4i128(<4 x i128> %d, <4 x i128> %e) {
15441659
; CHECK-SD-LABEL: xor_v4i128:
15451660
; CHECK-SD: // %bb.0: // %entry
1546-
; CHECK-SD-NEXT: ldp x9, x8, [sp, #32]
1547-
; CHECK-SD-NEXT: ldp x11, x10, [sp]
1548-
; CHECK-SD-NEXT: ldp x13, x12, [sp, #16]
1549-
; CHECK-SD-NEXT: ldp x15, x14, [sp, #48]
1550-
; CHECK-SD-NEXT: eor x4, x4, x9
1551-
; CHECK-SD-NEXT: eor x0, x0, x11
1552-
; CHECK-SD-NEXT: eor x1, x1, x10
1553-
; CHECK-SD-NEXT: eor x5, x5, x8
1554-
; CHECK-SD-NEXT: eor x2, x2, x13
1555-
; CHECK-SD-NEXT: eor x3, x3, x12
1556-
; CHECK-SD-NEXT: eor x6, x6, x15
1557-
; CHECK-SD-NEXT: eor x7, x7, x14
1661+
; CHECK-SD-NEXT: ldr d0, [sp]
1662+
; CHECK-SD-NEXT: fmov d2, x0
1663+
; CHECK-SD-NEXT: fmov d3, x2
1664+
; CHECK-SD-NEXT: fmov d5, x4
1665+
; CHECK-SD-NEXT: fmov d7, x6
1666+
; CHECK-SD-NEXT: add x8, sp, #8
1667+
; CHECK-SD-NEXT: ldr d1, [sp, #16]
1668+
; CHECK-SD-NEXT: ld1 { v0.d }[1], [x8]
1669+
; CHECK-SD-NEXT: add x8, sp, #24
1670+
; CHECK-SD-NEXT: ldr d4, [sp, #32]
1671+
; CHECK-SD-NEXT: ldr d6, [sp, #48]
1672+
; CHECK-SD-NEXT: mov v2.d[1], x1
1673+
; CHECK-SD-NEXT: ld1 { v1.d }[1], [x8]
1674+
; CHECK-SD-NEXT: mov v3.d[1], x3
1675+
; CHECK-SD-NEXT: add x8, sp, #40
1676+
; CHECK-SD-NEXT: mov v5.d[1], x5
1677+
; CHECK-SD-NEXT: add x9, sp, #56
1678+
; CHECK-SD-NEXT: mov v7.d[1], x7
1679+
; CHECK-SD-NEXT: ld1 { v4.d }[1], [x8]
1680+
; CHECK-SD-NEXT: ld1 { v6.d }[1], [x9]
1681+
; CHECK-SD-NEXT: eor v0.16b, v2.16b, v0.16b
1682+
; CHECK-SD-NEXT: eor v1.16b, v3.16b, v1.16b
1683+
; CHECK-SD-NEXT: eor v2.16b, v7.16b, v6.16b
1684+
; CHECK-SD-NEXT: eor v3.16b, v5.16b, v4.16b
1685+
; CHECK-SD-NEXT: mov x1, v0.d[1]
1686+
; CHECK-SD-NEXT: fmov x0, d0
1687+
; CHECK-SD-NEXT: mov x3, v1.d[1]
1688+
; CHECK-SD-NEXT: fmov x2, d1
1689+
; CHECK-SD-NEXT: mov x5, v3.d[1]
1690+
; CHECK-SD-NEXT: mov x7, v2.d[1]
1691+
; CHECK-SD-NEXT: fmov x4, d3
1692+
; CHECK-SD-NEXT: fmov x6, d2
15581693
; CHECK-SD-NEXT: ret
15591694
;
15601695
; CHECK-GI-LABEL: xor_v4i128:

0 commit comments

Comments
 (0)