Format adjustment and some bugfix

Author: BoyaoWang430

llvm/docs/ReleaseNotes.md

@@ -121,6 +121,7 @@ Changes to the RISC-V Backend
 * Ssctr and Smctr extensions are no longer experimental.
 * Add support for Zvfbfa (Additional BF16 vector compute support)
 * Adds experimental support for the 'Zibi` (Branch with Immediate) extension.
+
 Changes to the WebAssembly Backend
 ----------------------------------
 

llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td

@@ -1,4 +1,4 @@
-//===-- RISCVInstrInfoZibi.td - 'Zibi' instructions ------*- tablegen -*-===//
+//===-- RISCVInstrInfoZibi.td - 'Zibi' instructions --------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -9,6 +9,7 @@
 /// This file describes the RISC-V instructions for 'Zibi' (branch with imm).
 ///
 //===----------------------------------------------------------------------===//
+
 // A 5-bit unsigned immediate representing 1-31 and -1. 00000 represents -1.
 def uimm5_zibi : RISCVOp<XLenVT>, ImmLeaf<XLenVT, [{
     return (Imm != 0 && isUInt<5>(Imm)) || Imm == -1;
@@ -36,7 +37,8 @@ class Branch_imm<bits<3> funct3, string opcodestr>
   let mayLoad = 0;
   let mayStore = 0;
 }
+
 let Predicates = [HasStdExtZibi] in {
   def BEQI : Branch_imm<0b010, "beqi">;
   def BNEI : Branch_imm<0b011, "bnei">;
-} // Predicates = [HasStdExtZibi]
+} // Predicates = [HasStdExtZibi]

llvm/test/CodeGen/RISCV/attributes.ll

@@ -173,14 +173,9 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
-<<<<<<< HEAD
 ; RUN: llc -mtriple=riscv32 -mattr=+smctr  %s -o - | FileCheck --check-prefix=RV32SMCTR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+ssctr  %s -o - | FileCheck --check-prefix=RV32SSCTR %s
-=======
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-smctr  %s -o - | FileCheck --check-prefix=RV32SMCTR %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssctr  %s -o - | FileCheck --check-prefix=RV32SSCTR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibi %s -o - | FileCheck --check-prefix=RV32ZIBI %s
->>>>>>> aea8133a1fe3 ([RISCV][MC] Add MC support of Zibi experimental extension)
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -540,12 +535,8 @@
 ; RV32SUPM: .attribute 5, "rv32i2p1_supm1p0"
 ; RV32SMCTR: .attribute 5, "rv32i2p1_smctr1p0_sscsrind1p0"
 ; RV32SSCTR: .attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0"
-<<<<<<< HEAD
 ; RV32P: .attribute 5, "rv32i2p1_p0p15"
-=======
-; RV32P: .attribute 5, "rv32i2p1_p0p14"
 ; RV32ZIBI: .attribute 5, "rv32i2p1_zibi0p1"
->>>>>>> aea8133a1fe3 ([RISCV][MC] Add MC support of Zibi experimental extension)
 
 ; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"