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[RISCV][Xqcilo] Load/Store Pseudos
This adds `qc.e.l<type> <reg>, <symbol>` and `qc.e.s<type> <reg>, <symbol>, <reg>` pseudos for the corresponding Xqcilo instructions. These emit as an AUIPC + (Standard) Load/Store pair, because this sequence is shorter and can be relaxed back into the equivalent Xqcilo load/store instruction in the right circumstances.
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‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

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@@ -3746,18 +3746,23 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
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emitLoadTLSGDAddress(Inst, IDLoc, Out);
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return false;
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case RISCV::PseudoLB:
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case RISCV::PseudoQC_E_LB:
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emitLoadStoreSymbol(Inst, RISCV::LB, IDLoc, Out, /*HasTmpReg=*/false);
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return false;
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case RISCV::PseudoLBU:
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case RISCV::PseudoQC_E_LBU:
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emitLoadStoreSymbol(Inst, RISCV::LBU, IDLoc, Out, /*HasTmpReg=*/false);
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return false;
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case RISCV::PseudoLH:
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case RISCV::PseudoQC_E_LH:
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emitLoadStoreSymbol(Inst, RISCV::LH, IDLoc, Out, /*HasTmpReg=*/false);
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return false;
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case RISCV::PseudoLHU:
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case RISCV::PseudoQC_E_LHU:
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emitLoadStoreSymbol(Inst, RISCV::LHU, IDLoc, Out, /*HasTmpReg=*/false);
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return false;
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case RISCV::PseudoLW:
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case RISCV::PseudoQC_E_LW:
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emitLoadStoreSymbol(Inst, RISCV::LW, IDLoc, Out, /*HasTmpReg=*/false);
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return false;
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case RISCV::PseudoLWU:
@@ -3776,12 +3781,15 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
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emitLoadStoreSymbol(Inst, RISCV::FLD, IDLoc, Out, /*HasTmpReg=*/true);
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return false;
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case RISCV::PseudoSB:
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case RISCV::PseudoQC_E_SB:
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emitLoadStoreSymbol(Inst, RISCV::SB, IDLoc, Out, /*HasTmpReg=*/true);
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return false;
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case RISCV::PseudoSH:
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case RISCV::PseudoQC_E_SH:
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emitLoadStoreSymbol(Inst, RISCV::SH, IDLoc, Out, /*HasTmpReg=*/true);
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return false;
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case RISCV::PseudoSW:
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case RISCV::PseudoQC_E_SW:
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emitLoadStoreSymbol(Inst, RISCV::SW, IDLoc, Out, /*HasTmpReg=*/true);
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return false;
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case RISCV::PseudoSD:

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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@@ -1186,6 +1186,23 @@ def PseudoLongQC_E_BGEI : LongBcciPseudo<simm16nonzero, 10>;
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def PseudoLongQC_E_BLTUI : LongBcciPseudo<uimm16nonzero, 10>;
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def PseudoLongQC_E_BGEUI : LongBcciPseudo<uimm16nonzero, 10>;
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// Load/Store predicates with QC.E.* Mnemonics. These expand to an AUIPC +
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// (Standard) Load/Store pairs, as this sequence can materialize all 32-bit
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// addresses, and is shorter than e.g. an AUIPC + Xqcilo Load/Store pair.
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// These pairs can be turned back into Xqcilo instructions using linker
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// relaxation.
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let Predicates = [HasVendorXqcilo, IsRV32] in {
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def PseudoQC_E_LB : PseudoLoad<"qc.e.lb">;
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def PseudoQC_E_LBU : PseudoLoad<"qc.e.lbu">;
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def PseudoQC_E_LH : PseudoLoad<"qc.e.lh">;
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def PseudoQC_E_LHU : PseudoLoad<"qc.e.lhu">;
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def PseudoQC_E_LW : PseudoLoad<"qc.e.lw">;
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def PseudoQC_E_SB : PseudoStore<"qc.e.sb">;
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def PseudoQC_E_SH : PseudoStore<"qc.e.sh">;
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def PseudoQC_E_SW : PseudoStore<"qc.e.sw">;
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} // Predicates = [HasVendorXqcilo, IsRV32]
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//===----------------------------------------------------------------------===//
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// Code Gen Patterns
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//===----------------------------------------------------------------------===//

‎llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s‎

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# Xqcilo - Qualcomm uC Large Offset Load Store extension
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# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilo \
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# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ENABLED %s
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# RUN: not llvm-mc %s -triple=riscv32 -mattr=-experimental-xqcilo \
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# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-DISABLED %s
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# CHECK-ENABLED: [[@LINE+2]]:1: error: too few operands for instruction
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# CHECK-DISABLED: [[@LINE+1]]:1: error: too few operands for instruction
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qc.e.lb a0, 0xf000
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# CHECK-ENABLED: [[@LINE+2]]:1: error: too few operands for instruction
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# CHECK-DISABLED: [[@LINE+1]]:1: error: too few operands for instruction
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qc.e.lb a0, 0xf000
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# CHECK-ENABLED: [[@LINE+2]]:1: error: too few operands for instruction
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# CHECK-DISABLED: [[@LINE+1]]:1: error: too few operands for instruction
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qc.e.lbu a0, 0xf000
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# CHECK-ENABLED: [[@LINE+2]]:1: error: too few operands for instruction
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# CHECK-DISABLED: [[@LINE+1]]:1: error: too few operands for instruction
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qc.e.lh a0, 0xf000
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# CHECK-ENABLED: [[@LINE+2]]:1: error: too few operands for instruction
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# CHECK-DISABLED: [[@LINE+1]]:1: error: too few operands for instruction
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qc.e.lhu a0, 0xf000
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# CHECK-ENABLED: [[@LINE+2]]:1: error: too few operands for instruction
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# CHECK-DISABLED: [[@LINE+1]]:1: error: too few operands for instruction
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qc.e.lw a0, 0xf000
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# CHECK-ENABLED: [[@LINE+2]]:21: error: invalid operand for instruction
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# CHECK-DISABLED: [[@LINE+1]]:21: error: invalid operand for instruction
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qc.e.sb a0, 0xf000, t0
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# CHECK-ENABLED: [[@LINE+2]]:21: error: invalid operand for instruction
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# CHECK-DISABLED: [[@LINE+1]]:21: error: invalid operand for instruction
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qc.e.sh a0, 0xf000, t0
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# CHECK-ENABLED: [[@LINE+2]]:21: error: invalid operand for instruction
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# CHECK-DISABLED: [[@LINE+1]]:21: error: invalid operand for instruction
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qc.e.sw a0, 0xf000, t0
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# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
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qc.e.lb a0, undefined
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# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
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qc.e.lbu a0, undefined
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# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
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qc.e.lh a0, undefined
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# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
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qc.e.lhu a0, undefined
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# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
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qc.e.lw a0, undefined
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# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
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qc.e.sb a0, undefined, t0
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# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
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qc.e.sh a0, undefined, t0
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# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
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qc.e.sw a0, undefined, t0
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# CHECK-ENABLED: [[@LINE+2]]:1: error: too few operands for instruction
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# CHECK-DISABLED: [[@LINE+1]]:1: error: too few operands for instruction
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qc.e.sb a0, undefined
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# CHECK-ENABLED: [[@LINE+2]]:1: error: too few operands for instruction
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# CHECK-DISABLED: [[@LINE+1]]:1: error: too few operands for instruction
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qc.e.sh a0, undefined
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# CHECK-ENABLED: [[@LINE+2]]:1: error: too few operands for instruction
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# CHECK-DISABLED: [[@LINE+1]]:1: error: too few operands for instruction
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qc.e.sw a0, undefined

‎llvm/test/MC/RISCV/xqcilo-pseudos-valid.s‎

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# Xqcilo - Qualcomm uC Large Offset Load Store extension
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilo \
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# RUN: | FileCheck -check-prefixes=CHECK %s
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# CHECK-LABEL: .Lpcrel_hi0
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# CHECK-NEXT: auipc a0, %pcrel_hi(undefined)
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# CHECK-NEXT: lb a0, %pcrel_lo(.Lpcrel_hi0)(a0)
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qc.e.lb a0, undefined
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# CHECK-LABEL: .Lpcrel_hi1
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# CHECK-NEXT: auipc a0, %pcrel_hi(undefined)
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# CHECK-NEXT: lbu a0, %pcrel_lo(.Lpcrel_hi1)(a0)
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qc.e.lbu a0, undefined
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# CHECK-LABEL: .Lpcrel_hi2
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# CHECK-NEXT: auipc a0, %pcrel_hi(undefined)
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# CHECK-NEXT: lh a0, %pcrel_lo(.Lpcrel_hi2)(a0)
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qc.e.lh a0, undefined
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# CHECK-LABEL: .Lpcrel_hi3
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# CHECK-NEXT: auipc a0, %pcrel_hi(undefined)
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# CHECK-NEXT: lhu a0, %pcrel_lo(.Lpcrel_hi3)(a0)
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qc.e.lhu a0, undefined
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# CHECK-LABEL: .Lpcrel_hi4
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# CHECK-NEXT: auipc a0, %pcrel_hi(undefined)
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# CHECK-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi4)(a0)
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qc.e.lw a0, undefined
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# CHECK-LABEL: .Lpcrel_hi5
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# CHECK-NEXT: auipc t0, %pcrel_hi(undefined)
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# CHECK-NEXT: sb a0, %pcrel_lo(.Lpcrel_hi5)(t0)
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qc.e.sb a0, undefined, t0
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# CHECK-LABEL: .Lpcrel_hi6
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# CHECK-NEXT: auipc t0, %pcrel_hi(undefined)
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# CHECK-NEXT: sh a0, %pcrel_lo(.Lpcrel_hi6)(t0)
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qc.e.sh a0, undefined, t0
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# CHECK-LABEL: .Lpcrel_hi7
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# CHECK-NEXT: auipc t0, %pcrel_hi(undefined)
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# CHECK-NEXT: sw a0, %pcrel_lo(.Lpcrel_hi7)(t0)
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qc.e.sw a0, undefined, t0

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