[AArch64][SVE] Mark AES instructions commutable.

We are already doing this for the Neon versions of the instructions,
just not for SVE.

Author: rj-jesus

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

@@ -4064,8 +4064,8 @@ let Predicates = [HasSVE2_or_SME] in {
 
 let Predicates = [HasSVEAES, HasNonStreamingSVE2_or_SSVE_AES] in {
   // SVE2 crypto destructive binary operations
-  defm AESE_ZZZ_B : sve2_crypto_des_bin_op<0b00, "aese", ZPR8, int_aarch64_sve_aese, nxv16i8>;
-  defm AESD_ZZZ_B : sve2_crypto_des_bin_op<0b01, "aesd", ZPR8, int_aarch64_sve_aesd, nxv16i8>;
+  defm AESE_ZZZ_B : sve2_crypto_des_bin_op<0b00, "aese", ZPR8, int_aarch64_sve_aese, nxv16i8, /*commutable=*/1>;
+  defm AESD_ZZZ_B : sve2_crypto_des_bin_op<0b01, "aesd", ZPR8, int_aarch64_sve_aesd, nxv16i8, /*commutable=*/1>;
 
   // SVE2 crypto unary operations
   defm AESMC_ZZ_B  : sve2_crypto_unary_op<0b0, "aesmc",  int_aarch64_sve_aesmc>;

llvm/lib/Target/AArch64/SVEInstrFormats.td

@@ -9254,7 +9254,9 @@ class sve2_crypto_des_bin_op<bits<2> opc, string asm, ZPRRegOp zprty>
 }
 
 multiclass sve2_crypto_des_bin_op<bits<2> opc, string asm, ZPRRegOp zprty,
-                                  SDPatternOperator op, ValueType vt> {
+                                  SDPatternOperator op, ValueType vt,
+                                  bit commutable = 0> {
+  let isCommutable = commutable in
   def NAME : sve2_crypto_des_bin_op<opc, asm, zprty>;
   def : SVE_2_Op_Pat<vt, op, vt, vt, !cast<Instruction>(NAME)>;
 }

llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll

@@ -19,8 +19,7 @@ define <vscale x 16 x i8> @aesd_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
 define <vscale x 16 x i8> @aesd_i8_commuted(<vscale x 16 x i8> %a,
 ; CHECK-LABEL: aesd_i8_commuted:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    aesd z1.b, z1.b, z0.b
-; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    aesd z0.b, z0.b, z1.b
 ; CHECK-NEXT:    ret
                                             <vscale x 16 x i8> %b) {
   %out = call <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8> %b,
@@ -58,8 +57,7 @@ define <vscale x 16 x i8> @aese_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
 define <vscale x 16 x i8> @aese_i8_commuted(<vscale x 16 x i8> %a,
 ; CHECK-LABEL: aese_i8_commuted:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    aese z1.b, z1.b, z0.b
-; CHECK-NEXT:    mov z0.d, z1.d
+; CHECK-NEXT:    aese z0.b, z0.b, z1.b
 ; CHECK-NEXT:    ret
                                             <vscale x 16 x i8> %b) {
   %out = call <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8> %b,