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[SPIR-V] Fix block sorting with irreducible CFG (#116996)
Block sorting was assuming reducible CFG. Meaning we always had a best node to continue with. Irreducible CFG makes breaks this assumption, so the algorithm looped indefinitely because no node was a valid candidate. Fixes #116692 --------- Signed-off-by: Nathan Gauër <[email protected]>
1 parent c952f0e commit 53326ee

33 files changed

+1245
-816
lines changed

‎llvm/lib/Target/SPIRV/SPIRVUtils.cpp

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -635,15 +635,12 @@ bool sortBlocks(Function &F) {
635635
return false;
636636

637637
bool Modified = false;
638-
639638
std::vector<BasicBlock *> Order;
640639
Order.reserve(F.size());
641640

642-
PartialOrderingVisitor Visitor(F);
643-
Visitor.partialOrderVisit(*F.begin(), [&Order](BasicBlock *Block) {
644-
Order.push_back(Block);
645-
return true;
646-
});
641+
ReversePostOrderTraversal<Function *> RPOT(&F);
642+
for (BasicBlock *BB : RPOT)
643+
Order.push_back(BB);
647644

648645
assert(&*F.begin() == Order[0]);
649646
BasicBlock *LastBlock = &*F.begin();

‎llvm/test/CodeGen/SPIRV/branching/OpSwitchBranches.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -34,16 +34,16 @@ end:
3434
%result = load i32, ptr %alloc
3535
ret i32 %result
3636

37-
; CHECK-SPIRV: %[[#DEFAULT]] = OpLabel
37+
; CHECK-SPIRV: %[[#CASE3]] = OpLabel
3838
; CHECK-SPIRV: OpBranch %[[#END:]]
3939

40-
; CHECK-SPIRV: %[[#CASE1]] = OpLabel
40+
; CHECK-SPIRV: %[[#CASE2]] = OpLabel
4141
; CHECK-SPIRV: OpBranch %[[#END]]
4242

43-
; CHECK-SPIRV: %[[#CASE2]] = OpLabel
43+
; CHECK-SPIRV: %[[#CASE1]] = OpLabel
4444
; CHECK-SPIRV: OpBranch %[[#END]]
4545

46-
; CHECK-SPIRV: %[[#CASE3]] = OpLabel
46+
; CHECK-SPIRV: %[[#DEFAULT]] = OpLabel
4747
; CHECK-SPIRV: OpBranch %[[#END]]
4848

4949
; CHECK-SPIRV: %[[#END]] = OpLabel

‎llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,14 +12,13 @@ define void @test_switch_with_unreachable_block(i1 %a) {
1212
i32 1, label %reachable
1313
]
1414

15-
; CHECK-SPIRV: %[[#UNREACHABLE]] = OpLabel
16-
; CHECK-SPIRV-NEXT: OpUnreachable
17-
1815
; CHECK-SPIRV-NEXT: %[[#REACHABLE]] = OpLabel
1916
reachable:
2017
; CHECK-SPIRV-NEXT: OpReturn
2118
ret void
2219

20+
; CHECK-SPIRV: %[[#UNREACHABLE]] = OpLabel
21+
; CHECK-SPIRV-NEXT: OpUnreachable
2322
unreachable:
2423
unreachable
2524
}

‎llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,19 +32,19 @@ case4:
3232
default2:
3333
ret void
3434

35-
; CHECK-SPIRV: %[[#CASE1]] = OpLabel
35+
; CHECK-SPIRV: %[[#CASE2]] = OpLabel
3636
; CHECK-SPIRV-NEXT: OpBranch %[[#DEFAULT1]]
3737

38-
; CHECK-SPIRV: %[[#CASE2]] = OpLabel
38+
; CHECK-SPIRV: %[[#CASE1]] = OpLabel
3939
; CHECK-SPIRV-NEXT: OpBranch %[[#DEFAULT1]]
4040

4141
; CHECK-SPIRV: %[[#DEFAULT1]] = OpLabel
4242
; CHECK-SPIRV-NEXT: OpSwitch %[[#REGISTER]] %[[#DEFAULT2:]] 0 %[[#CASE3:]] 1 %[[#CASE4:]]
4343

44-
; CHECK-SPIRV: %[[#CASE3]] = OpLabel
44+
; CHECK-SPIRV: %[[#CASE4]] = OpLabel
4545
; CHECK-SPIRV-NEXT: OpBranch %[[#DEFAULT2]]
4646

47-
; CHECK-SPIRV: %[[#CASE4:]] = OpLabel
47+
; CHECK-SPIRV: %[[#CASE3]] = OpLabel
4848
; CHECK-SPIRV-NEXT: OpBranch %[[#DEFAULT2]]
4949

5050
; CHECK-SPIRV: %[[#DEFAULT2]] = OpLabel

‎llvm/test/CodeGen/SPIRV/branching/if-merging.ll

Lines changed: 16 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
; CHECK-DAG: OpName [[FOO:%.+]] "foo"
66
; CHECK-DAG: OpName [[BAR:%.+]] "bar"
77

8-
; CHECK-DAG: [[I32:%.+]] = OpTypeInt 32
9-
; CHECK-DAG: [[BOOL:%.+]] = OpTypeBool
8+
; CHECK-DAG: %[[#I32:]] = OpTypeInt 32
9+
; CHECK-DAG: %[[#BOOL:]] = OpTypeBool
1010

1111
declare i32 @foo()
1212
declare i32 @bar()
@@ -30,23 +30,24 @@ merge_label:
3030
}
3131

3232
; CHECK: OpFunction
33-
; CHECK: [[A:%.+]] = OpFunctionParameter [[I32]]
34-
; CHECK: [[B:%.+]] = OpFunctionParameter [[I32]]
33+
; CHECK: %[[#A:]] = OpFunctionParameter %[[#I32]]
34+
; CHECK: %[[#B:]] = OpFunctionParameter %[[#I32]]
3535

36-
; CHECK: [[ENTRY:%.+]] = OpLabel
37-
; CHECK: [[COND:%.+]] = OpIEqual [[BOOL]] [[A]] [[B]]
38-
; CHECK: OpBranchConditional [[COND]] [[TRUE_LABEL:%.+]] [[FALSE_LABEL:%.+]]
36+
; CHECK: %[[#ENTRY:]] = OpLabel
37+
; CHECK: %[[#COND:]] = OpIEqual %[[#BOOL]] %[[#A]] %[[#B]]
38+
; CHECK: OpBranchConditional %[[#COND]] %[[#TRUE_LABEL:]] %[[#FALSE_LABEL:]]
3939

40-
; CHECK: [[TRUE_LABEL]] = OpLabel
41-
; CHECK: [[V1:%.+]] = OpFunctionCall [[I32]] [[FOO]]
42-
; CHECK: OpBranch [[MERGE_LABEL:%.+]]
40+
; CHECK: %[[#FALSE_LABEL]] = OpLabel
41+
; CHECK: %[[#V2:]] = OpFunctionCall %[[#I32]] [[BAR]]
42+
; CHECK: OpBranch %[[#MERGE_LABEL:]]
4343

44-
; CHECK: [[FALSE_LABEL]] = OpLabel
45-
; CHECK: [[V2:%.+]] = OpFunctionCall [[I32]] [[BAR]]
46-
; CHECK: OpBranch [[MERGE_LABEL]]
44+
; CHECK: %[[#TRUE_LABEL]] = OpLabel
45+
; CHECK: %[[#V1:]] = OpFunctionCall %[[#I32]] [[FOO]]
46+
; CHECK: OpBranch %[[#MERGE_LABEL]]
4747

48-
; CHECK: [[MERGE_LABEL]] = OpLabel
49-
; CHECK-NEXT: [[V:%.+]] = OpPhi [[I32]] [[V1]] [[TRUE_LABEL]] [[V2]] [[FALSE_LABEL]]
48+
49+
; CHECK: %[[#MERGE_LABEL]] = OpLabel
50+
; CHECK-NEXT: [[V:%.+]] = OpPhi %[[#I32]] %[[#V1]] %[[#TRUE_LABEL]] %[[#V2]] %[[#FALSE_LABEL]]
5051
; CHECK: OpReturnValue [[V]]
5152

5253
; CHECK-NEXT: OpFunctionEnd

‎llvm/test/CodeGen/SPIRV/branching/if-non-merging.ll

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,9 @@ false_label:
2121
; CHECK: [[ENTRY:%.+]] = OpLabel
2222
; CHECK: [[COND:%.+]] = OpIEqual [[BOOL]] [[A]] [[B]]
2323
; CHECK: OpBranchConditional [[COND]] [[TRUE_LABEL:%.+]] [[FALSE_LABEL:%.+]]
24-
; CHECK: [[TRUE_LABEL]] = OpLabel
25-
; CHECK: OpReturnValue [[TRUE]]
24+
2625
; CHECK: [[FALSE_LABEL]] = OpLabel
2726
; CHECK: OpReturnValue [[FALSE]]
27+
28+
; CHECK: [[TRUE_LABEL]] = OpLabel
29+
; CHECK: OpReturnValue [[TRUE]]

‎llvm/test/CodeGen/SPIRV/instructions/ret-type.ll

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,10 +2,6 @@
22
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown --translator-compatibility-mode %s -o - -filetype=obj | spirv-val %}
33
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
44

5-
; Modifying the block ordering prevents the pointer types to correctly be deduced. Not sure why, but looks
6-
; orthogonal to the block sorting.
7-
; XFAIL: *
8-
95
; CHECK-DAG: OpName %[[Test1:.*]] "test1"
106
; CHECK-DAG: OpName %[[Foo:.*]] "foo"
117
; CHECK-DAG: OpName %[[Bar:.*]] "bar"

‎llvm/test/CodeGen/SPIRV/structurizer/basic-if.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -14,18 +14,18 @@ entry:
1414
%1 = alloca i32, align 4
1515
br i1 true, label %left, label %right
1616

17-
; CHECK: %[[#left]] = OpLabel
18-
; CHECK: OpBranch %[[#merge]]
19-
left:
20-
store i32 0, ptr %1
21-
br label %end
22-
2317
; CHECK: %[[#right]] = OpLabel
2418
; CHECK: OpBranch %[[#merge]]
2519
right:
2620
store i32 0, ptr %1
2721
br label %end
2822

23+
; CHECK: %[[#left]] = OpLabel
24+
; CHECK: OpBranch %[[#merge]]
25+
left:
26+
store i32 0, ptr %1
27+
br label %end
28+
2929
; CHECK: %[[#merge]] = OpLabel
3030
; CHECK: OpReturnValue %[[#]]
3131
end:

‎llvm/test/CodeGen/SPIRV/structurizer/basic-loop.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,11 @@ header:
2121
%2 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ]
2222
br i1 true, label %body, label %merge
2323

24+
; CHECK: %[[#merge]] = OpLabel
25+
; CHECK: OpReturnValue %[[#]]
26+
merge:
27+
ret i32 0
28+
2429
; CHECK: %[[#body]] = OpLabel
2530
; CHECK: OpBranch %[[#continue]]
2631
body:
@@ -31,11 +36,6 @@ continue:
3136
br label %header
3237
; CHECK: %[[#continue]] = OpLabel
3338
; CHECK: OpBranch %[[#header]]
34-
35-
; CHECK: %[[#merge]] = OpLabel
36-
; CHECK: OpReturnValue %[[#]]
37-
merge:
38-
ret i32 0
3939
}
4040

4141
; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)

‎llvm/test/CodeGen/SPIRV/structurizer/basic-phi.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -18,18 +18,18 @@ entry:
1818
%0 = call token @llvm.experimental.convergence.entry()
1919
br i1 true, label %left, label %right
2020

21-
; CHECK: %[[#left]] = OpLabel
22-
; CHECK-NEXT: OpStore %[[#var]] %[[#int_0]]
23-
; CHECK-NEXT: OpBranch %[[#merge]]
24-
left:
25-
br label %end
26-
2721
; CHECK: %[[#right]] = OpLabel
2822
; CHECK-NEXT: OpStore %[[#var]] %[[#int_1]]
2923
; CHECK-NEXT: OpBranch %[[#merge]]
3024
right:
3125
br label %end
3226

27+
; CHECK: %[[#left]] = OpLabel
28+
; CHECK-NEXT: OpStore %[[#var]] %[[#int_0]]
29+
; CHECK-NEXT: OpBranch %[[#merge]]
30+
left:
31+
br label %end
32+
3333
; CHECK: %[[#merge]] = OpLabel
3434
; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#var]]
3535
; CHECK: OpReturnValue %[[#tmp]]

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