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Revert "[AArch64] Run optimizeTerminators earlier too." (#171505)
Reverts #170907 Causes crashes, see #170907 (comment)
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12 files changed

+199
-144
lines changed

12 files changed

+199
-144
lines changed

‎llvm/lib/CodeGen/ShrinkWrap.cpp‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -618,8 +618,6 @@ bool ShrinkWrapImpl::postShrinkWrapping(bool HasCandidate, MachineFunction &MF,
618618

619619
DenseSet<const MachineBasicBlock *> DirtyBBs;
620620
for (MachineBasicBlock &MBB : MF) {
621-
if (!MDT->isReachableFromEntry(&MBB))
622-
continue;
623621
if (MBB.isEHPad()) {
624622
DirtyBBs.insert(&MBB);
625623
continue;

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 0 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -708,53 +708,6 @@ unsigned AArch64InstrInfo::insertBranch(
708708
return 2;
709709
}
710710

711-
bool llvm::optimizeTerminators(MachineBasicBlock *MBB,
712-
const TargetInstrInfo &TII) {
713-
for (MachineInstr &MI : MBB->terminators()) {
714-
unsigned Opc = MI.getOpcode();
715-
switch (Opc) {
716-
case AArch64::CBZW:
717-
case AArch64::CBZX:
718-
case AArch64::TBZW:
719-
case AArch64::TBZX:
720-
// CBZ/TBZ with WZR/XZR -> unconditional B
721-
if (MI.getOperand(0).getReg() == AArch64::WZR ||
722-
MI.getOperand(0).getReg() == AArch64::XZR) {
723-
DEBUG_WITH_TYPE("optimizeTerminators",
724-
dbgs() << "Removing always taken branch: " << MI);
725-
MachineBasicBlock *Target = TII.getBranchDestBlock(MI);
726-
SmallVector<MachineBasicBlock *> Succs(MBB->successors());
727-
for (auto *S : Succs)
728-
if (S != Target)
729-
MBB->removeSuccessor(S);
730-
DebugLoc DL = MI.getDebugLoc();
731-
while (MBB->rbegin() != &MI)
732-
MBB->rbegin()->eraseFromParent();
733-
MI.eraseFromParent();
734-
BuildMI(MBB, DL, TII.get(AArch64::B)).addMBB(Target);
735-
return true;
736-
}
737-
break;
738-
case AArch64::CBNZW:
739-
case AArch64::CBNZX:
740-
case AArch64::TBNZW:
741-
case AArch64::TBNZX:
742-
// CBNZ/TBNZ with WZR/XZR -> never taken, remove branch and successor
743-
if (MI.getOperand(0).getReg() == AArch64::WZR ||
744-
MI.getOperand(0).getReg() == AArch64::XZR) {
745-
DEBUG_WITH_TYPE("optimizeTerminators",
746-
dbgs() << "Removing never taken branch: " << MI);
747-
MachineBasicBlock *Target = TII.getBranchDestBlock(MI);
748-
MI.getParent()->removeSuccessor(Target);
749-
MI.eraseFromParent();
750-
return true;
751-
}
752-
break;
753-
}
754-
}
755-
return false;
756-
}
757-
758711
// Find the original register that VReg is copied from.
759712
static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) {
760713
while (Register::isVirtualRegister(VReg)) {

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -705,8 +705,6 @@ int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset,
705705
unsigned *OutUnscaledOp = nullptr,
706706
int64_t *EmittableOffset = nullptr);
707707

708-
bool optimizeTerminators(MachineBasicBlock *MBB, const TargetInstrInfo &TII);
709-
710708
static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
711709

712710
static inline bool isCondBranchOpcode(int Opc) {

‎llvm/lib/Target/AArch64/AArch64RedundantCondBranchPass.cpp‎

Lines changed: 45 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@
1414
//===----------------------------------------------------------------------===//
1515

1616
#include "AArch64.h"
17-
#include "AArch64InstrInfo.h"
1817
#include "llvm/CodeGen/MachineFunctionPass.h"
1918
#include "llvm/CodeGen/MachineInstrBuilder.h"
2019
#include "llvm/CodeGen/TargetInstrInfo.h"
@@ -46,6 +45,51 @@ INITIALIZE_PASS(AArch64RedundantCondBranch, "aarch64-redundantcondbranch",
4645
"AArch64 Redundant Conditional Branch Elimination pass", false,
4746
false)
4847

48+
static bool optimizeTerminators(MachineBasicBlock *MBB,
49+
const TargetInstrInfo &TII) {
50+
for (MachineInstr &MI : make_early_inc_range(MBB->terminators())) {
51+
unsigned Opc = MI.getOpcode();
52+
switch (Opc) {
53+
case AArch64::CBZW:
54+
case AArch64::CBZX:
55+
case AArch64::TBZW:
56+
case AArch64::TBZX:
57+
// CBZ/TBZ with WZR/XZR -> unconditional B
58+
if (MI.getOperand(0).getReg() == AArch64::WZR ||
59+
MI.getOperand(0).getReg() == AArch64::XZR) {
60+
LLVM_DEBUG(dbgs() << "Removing redundant branch: " << MI);
61+
MachineBasicBlock *Target = TII.getBranchDestBlock(MI);
62+
SmallVector<MachineBasicBlock *> Succs(MBB->successors());
63+
for (auto *S : Succs)
64+
if (S != Target)
65+
MBB->removeSuccessor(S);
66+
DebugLoc DL = MI.getDebugLoc();
67+
while (MBB->rbegin() != &MI)
68+
MBB->rbegin()->eraseFromParent();
69+
MI.eraseFromParent();
70+
BuildMI(MBB, DL, TII.get(AArch64::B)).addMBB(Target);
71+
return true;
72+
}
73+
break;
74+
case AArch64::CBNZW:
75+
case AArch64::CBNZX:
76+
case AArch64::TBNZW:
77+
case AArch64::TBNZX:
78+
// CBNZ/TBNZ with WZR/XZR -> never taken, remove branch and successor
79+
if (MI.getOperand(0).getReg() == AArch64::WZR ||
80+
MI.getOperand(0).getReg() == AArch64::XZR) {
81+
LLVM_DEBUG(dbgs() << "Removing redundant branch: " << MI);
82+
MachineBasicBlock *Target = TII.getBranchDestBlock(MI);
83+
MI.getParent()->removeSuccessor(Target);
84+
MI.eraseFromParent();
85+
return true;
86+
}
87+
break;
88+
}
89+
}
90+
return false;
91+
}
92+
4993
bool AArch64RedundantCondBranch::runOnMachineFunction(MachineFunction &MF) {
5094
if (skipFunction(MF.getFunction()))
5195
return false;

‎llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,6 @@
5050
// to use WZR/XZR directly in some cases.
5151
//===----------------------------------------------------------------------===//
5252
#include "AArch64.h"
53-
#include "AArch64InstrInfo.h"
5453
#include "llvm/ADT/SetVector.h"
5554
#include "llvm/ADT/Statistic.h"
5655
#include "llvm/ADT/iterator_range.h"
@@ -476,7 +475,6 @@ bool AArch64RedundantCopyElimination::runOnMachineFunction(
476475
return false;
477476
TRI = MF.getSubtarget().getRegisterInfo();
478477
MRI = &MF.getRegInfo();
479-
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
480478

481479
// Resize the clobbered and used register unit trackers. We do this once per
482480
// function.
@@ -486,10 +484,8 @@ bool AArch64RedundantCopyElimination::runOnMachineFunction(
486484
OptBBUsedRegs.init(*TRI);
487485

488486
bool Changed = false;
489-
for (MachineBasicBlock &MBB : MF) {
490-
Changed |= optimizeTerminators(&MBB, TII);
487+
for (MachineBasicBlock &MBB : MF)
491488
Changed |= optimizeBlock(&MBB);
492-
}
493489
return Changed;
494490
}
495491

‎llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll‎

Lines changed: 52 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -735,15 +735,21 @@ define void @infiniteloop() {
735735
; ENABLE-NEXT: .cfi_offset w29, -16
736736
; ENABLE-NEXT: .cfi_offset w19, -24
737737
; ENABLE-NEXT: .cfi_offset w20, -32
738+
; ENABLE-NEXT: ; %bb.1: ; %if.then
738739
; ENABLE-NEXT: sub x19, sp, #16
739740
; ENABLE-NEXT: mov sp, x19
740741
; ENABLE-NEXT: mov w20, wzr
741-
; ENABLE-NEXT: LBB10_1: ; %for.body
742+
; ENABLE-NEXT: LBB10_2: ; %for.body
742743
; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1
743744
; ENABLE-NEXT: bl _something
744745
; ENABLE-NEXT: add w20, w0, w20
745746
; ENABLE-NEXT: str w20, [x19]
746-
; ENABLE-NEXT: b LBB10_1
747+
; ENABLE-NEXT: b LBB10_2
748+
; ENABLE-NEXT: ; %bb.3: ; %if.end
749+
; ENABLE-NEXT: sub sp, x29, #16
750+
; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
751+
; ENABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
752+
; ENABLE-NEXT: ret
747753
;
748754
; DISABLE-LABEL: infiniteloop:
749755
; DISABLE: ; %bb.0: ; %entry
@@ -755,15 +761,21 @@ define void @infiniteloop() {
755761
; DISABLE-NEXT: .cfi_offset w29, -16
756762
; DISABLE-NEXT: .cfi_offset w19, -24
757763
; DISABLE-NEXT: .cfi_offset w20, -32
764+
; DISABLE-NEXT: ; %bb.1: ; %if.then
758765
; DISABLE-NEXT: sub x19, sp, #16
759766
; DISABLE-NEXT: mov sp, x19
760767
; DISABLE-NEXT: mov w20, wzr
761-
; DISABLE-NEXT: LBB10_1: ; %for.body
768+
; DISABLE-NEXT: LBB10_2: ; %for.body
762769
; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1
763770
; DISABLE-NEXT: bl _something
764771
; DISABLE-NEXT: add w20, w0, w20
765772
; DISABLE-NEXT: str w20, [x19]
766-
; DISABLE-NEXT: b LBB10_1
773+
; DISABLE-NEXT: b LBB10_2
774+
; DISABLE-NEXT: ; %bb.3: ; %if.end
775+
; DISABLE-NEXT: sub sp, x29, #16
776+
; DISABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
777+
; DISABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
778+
; DISABLE-NEXT: ret
767779
entry:
768780
br i1 undef, label %if.then, label %if.end
769781

@@ -794,10 +806,11 @@ define void @infiniteloop2() {
794806
; ENABLE-NEXT: .cfi_offset w29, -16
795807
; ENABLE-NEXT: .cfi_offset w19, -24
796808
; ENABLE-NEXT: .cfi_offset w20, -32
809+
; ENABLE-NEXT: ; %bb.1: ; %if.then
797810
; ENABLE-NEXT: sub x8, sp, #16
798811
; ENABLE-NEXT: mov sp, x8
799812
; ENABLE-NEXT: mov w9, wzr
800-
; ENABLE-NEXT: LBB11_1: ; %for.body
813+
; ENABLE-NEXT: LBB11_2: ; %for.body
801814
; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1
802815
; ENABLE-NEXT: ; InlineAsm Start
803816
; ENABLE-NEXT: mov x10, #0 ; =0x0
@@ -808,7 +821,12 @@ define void @infiniteloop2() {
808821
; ENABLE-NEXT: ; InlineAsm Start
809822
; ENABLE-NEXT: nop
810823
; ENABLE-NEXT: ; InlineAsm End
811-
; ENABLE-NEXT: b LBB11_1
824+
; ENABLE-NEXT: b LBB11_2
825+
; ENABLE-NEXT: ; %bb.3: ; %if.end
826+
; ENABLE-NEXT: sub sp, x29, #16
827+
; ENABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
828+
; ENABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
829+
; ENABLE-NEXT: ret
812830
;
813831
; DISABLE-LABEL: infiniteloop2:
814832
; DISABLE: ; %bb.0: ; %entry
@@ -820,10 +838,11 @@ define void @infiniteloop2() {
820838
; DISABLE-NEXT: .cfi_offset w29, -16
821839
; DISABLE-NEXT: .cfi_offset w19, -24
822840
; DISABLE-NEXT: .cfi_offset w20, -32
841+
; DISABLE-NEXT: ; %bb.1: ; %if.then
823842
; DISABLE-NEXT: sub x8, sp, #16
824843
; DISABLE-NEXT: mov sp, x8
825844
; DISABLE-NEXT: mov w9, wzr
826-
; DISABLE-NEXT: LBB11_1: ; %for.body
845+
; DISABLE-NEXT: LBB11_2: ; %for.body
827846
; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1
828847
; DISABLE-NEXT: ; InlineAsm Start
829848
; DISABLE-NEXT: mov x10, #0 ; =0x0
@@ -834,7 +853,12 @@ define void @infiniteloop2() {
834853
; DISABLE-NEXT: ; InlineAsm Start
835854
; DISABLE-NEXT: nop
836855
; DISABLE-NEXT: ; InlineAsm End
837-
; DISABLE-NEXT: b LBB11_1
856+
; DISABLE-NEXT: b LBB11_2
857+
; DISABLE-NEXT: ; %bb.3: ; %if.end
858+
; DISABLE-NEXT: sub sp, x29, #16
859+
; DISABLE-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
860+
; DISABLE-NEXT: ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
861+
; DISABLE-NEXT: ret
838862
entry:
839863
br i1 undef, label %if.then, label %if.end
840864

@@ -865,43 +889,49 @@ if.end:
865889
define void @infiniteloop3() {
866890
; ENABLE-LABEL: infiniteloop3:
867891
; ENABLE: ; %bb.0: ; %entry
892+
; ENABLE-NEXT: ; %bb.1: ; %loop2a.preheader
868893
; ENABLE-NEXT: mov x8, xzr
869894
; ENABLE-NEXT: mov x9, xzr
870895
; ENABLE-NEXT: mov x11, xzr
871-
; ENABLE-NEXT: b LBB12_2
872-
; ENABLE-NEXT: LBB12_1: ; %loop2b
873-
; ENABLE-NEXT: ; in Loop: Header=BB12_2 Depth=1
896+
; ENABLE-NEXT: b LBB12_3
897+
; ENABLE-NEXT: LBB12_2: ; %loop2b
898+
; ENABLE-NEXT: ; in Loop: Header=BB12_3 Depth=1
874899
; ENABLE-NEXT: str x10, [x11]
875900
; ENABLE-NEXT: mov x11, x10
876-
; ENABLE-NEXT: LBB12_2: ; %loop1
901+
; ENABLE-NEXT: LBB12_3: ; %loop1
877902
; ENABLE-NEXT: ; =>This Inner Loop Header: Depth=1
878903
; ENABLE-NEXT: mov x10, x9
879904
; ENABLE-NEXT: ldr x9, [x8]
880-
; ENABLE-NEXT: cbnz x8, LBB12_1
881-
; ENABLE-NEXT: ; %bb.3: ; in Loop: Header=BB12_2 Depth=1
905+
; ENABLE-NEXT: cbnz x8, LBB12_2
906+
; ENABLE-NEXT: ; %bb.4: ; in Loop: Header=BB12_3 Depth=1
882907
; ENABLE-NEXT: mov x8, x10
883908
; ENABLE-NEXT: mov x11, x10
884-
; ENABLE-NEXT: b LBB12_2
909+
; ENABLE-NEXT: b LBB12_3
910+
; ENABLE-NEXT: ; %bb.5: ; %end
911+
; ENABLE-NEXT: ret
885912
;
886913
; DISABLE-LABEL: infiniteloop3:
887914
; DISABLE: ; %bb.0: ; %entry
915+
; DISABLE-NEXT: ; %bb.1: ; %loop2a.preheader
888916
; DISABLE-NEXT: mov x8, xzr
889917
; DISABLE-NEXT: mov x9, xzr
890918
; DISABLE-NEXT: mov x11, xzr
891-
; DISABLE-NEXT: b LBB12_2
892-
; DISABLE-NEXT: LBB12_1: ; %loop2b
893-
; DISABLE-NEXT: ; in Loop: Header=BB12_2 Depth=1
919+
; DISABLE-NEXT: b LBB12_3
920+
; DISABLE-NEXT: LBB12_2: ; %loop2b
921+
; DISABLE-NEXT: ; in Loop: Header=BB12_3 Depth=1
894922
; DISABLE-NEXT: str x10, [x11]
895923
; DISABLE-NEXT: mov x11, x10
896-
; DISABLE-NEXT: LBB12_2: ; %loop1
924+
; DISABLE-NEXT: LBB12_3: ; %loop1
897925
; DISABLE-NEXT: ; =>This Inner Loop Header: Depth=1
898926
; DISABLE-NEXT: mov x10, x9
899927
; DISABLE-NEXT: ldr x9, [x8]
900-
; DISABLE-NEXT: cbnz x8, LBB12_1
901-
; DISABLE-NEXT: ; %bb.3: ; in Loop: Header=BB12_2 Depth=1
928+
; DISABLE-NEXT: cbnz x8, LBB12_2
929+
; DISABLE-NEXT: ; %bb.4: ; in Loop: Header=BB12_3 Depth=1
902930
; DISABLE-NEXT: mov x8, x10
903931
; DISABLE-NEXT: mov x11, x10
904-
; DISABLE-NEXT: b LBB12_2
932+
; DISABLE-NEXT: b LBB12_3
933+
; DISABLE-NEXT: ; %bb.5: ; %end
934+
; DISABLE-NEXT: ret
905935
entry:
906936
br i1 undef, label %loop2a, label %body
907937

‎llvm/test/CodeGen/AArch64/block-placement-optimize-branches.ll‎

Lines changed: 22 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -8,14 +8,20 @@
88
define i8 @foo_optsize(i32 %v4) optsize {
99
; CHECK-LABEL: foo_optsize:
1010
; CHECK: // %bb.0: // %entry
11-
; CHECK-NEXT: cbnz w0, .LBB0_2
12-
; CHECK-NEXT: // %bb.1: // %b2
13-
; CHECK-NEXT: mov w0, #1 // =0x1
11+
; CHECK-NEXT: b .LBB0_2
12+
; CHECK-NEXT: .LBB0_1:
13+
; CHECK-NEXT: mov w0, wzr
1414
; CHECK-NEXT: ret
1515
; CHECK-NEXT: .LBB0_2: // %b1
16-
; CHECK-NEXT: cmp w0, #1
17-
; CHECK-NEXT: mov w0, wzr
16+
; CHECK-NEXT: cbnz w0, .LBB0_4
17+
; CHECK-NEXT: // %bb.3: // %b2
18+
; CHECK-NEXT: mov w0, #1 // =0x1
1819
; CHECK-NEXT: ret
20+
; CHECK-NEXT: .LBB0_4: // %b1
21+
; CHECK-NEXT: cmp w0, #1
22+
; CHECK-NEXT: b.ne .LBB0_1
23+
; CHECK-NEXT: // %bb.5: // %b3
24+
; CHECK-NEXT: b .LBB0_1
1925
entry:
2026
%v2 = icmp eq i32 0, 0
2127
br i1 %v2, label %b1, label %b4
@@ -41,14 +47,20 @@ b4:
4147
define i8 @foo_optspeed(i32 %v4) {
4248
; CHECK-LABEL: foo_optspeed:
4349
; CHECK: // %bb.0: // %entry
44-
; CHECK-NEXT: cbnz w0, .LBB1_2
45-
; CHECK-NEXT: // %bb.1: // %b2
46-
; CHECK-NEXT: mov w0, #1 // =0x1
50+
; CHECK-NEXT: b .LBB1_2
51+
; CHECK-NEXT: .LBB1_1:
52+
; CHECK-NEXT: mov w0, wzr
4753
; CHECK-NEXT: ret
4854
; CHECK-NEXT: .LBB1_2: // %b1
49-
; CHECK-NEXT: cmp w0, #1
50-
; CHECK-NEXT: mov w0, wzr
55+
; CHECK-NEXT: cbnz w0, .LBB1_4
56+
; CHECK-NEXT: // %bb.3: // %b2
57+
; CHECK-NEXT: mov w0, #1 // =0x1
5158
; CHECK-NEXT: ret
59+
; CHECK-NEXT: .LBB1_4: // %b1
60+
; CHECK-NEXT: cmp w0, #1
61+
; CHECK-NEXT: b.ne .LBB1_1
62+
; CHECK-NEXT: // %bb.5: // %b3
63+
; CHECK-NEXT: b .LBB1_1
5264
entry:
5365
%v2 = icmp eq i32 0, 0
5466
br i1 %v2, label %b1, label %b4

‎llvm/test/CodeGen/AArch64/lr-reserved-for-ra-live-in.ll‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,10 @@ define i32 @check_lr_liveness(ptr %arg) #1 {
2121
; CHECK-NEXT: B %bb.3
2222
; CHECK-NEXT: {{ $}}
2323
; CHECK-NEXT: bb.1.bb:
24+
; CHECK-NEXT: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
2425
; CHECK-NEXT: liveins: $w0, $lr
2526
; CHECK-NEXT: {{ $}}
27+
; CHECK-NEXT: CBNZW $wzr, %bb.3
2628
; CHECK-NEXT: B %bb.2
2729
; CHECK-NEXT: {{ $}}
2830
; CHECK-NEXT: bb.2.bb1:

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