drop pure

Hardcode84 · Hardcode84 · commit 53fc37b2e845 · 2025-08-07T19:35:55.000+02:00
diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -189,7 +189,7 @@ def ROCDL_BallotOp :
   let assemblyFormat = "$pred attr-dict `:` type($res)";
 }
 
-def ROCDL_ReadfirstlaneOp : ROCDL_IntrOp<"readfirstlane", [], [0], [AllTypesMatch<["res", "src"]>, Pure], 1>,
+def ROCDL_ReadfirstlaneOp : ROCDL_IntrOp<"readfirstlane", [], [0], [AllTypesMatch<["res", "src"]>], 1>,
   Arguments<(ins LLVM_Type:$src)> {
   let results = (outs LLVM_Type:$res);
   let summary = "Get the value in first active lane.";

Original file line number	Diff line number	Diff line change
`@@ -189,7 +189,7 @@ def ROCDL_BallotOp :`
`189`	`189`	let assemblyFormat = "$pred attr-dict `:` type($res)";
`190`	`190`	`}`
`191`	`191`
`192`		`-def ROCDL_ReadfirstlaneOp : ROCDL_IntrOp<"readfirstlane", [], [0], [AllTypesMatch<["res", "src"]>, Pure], 1>,`
	`192`	`+def ROCDL_ReadfirstlaneOp : ROCDL_IntrOp<"readfirstlane", [], [0], [AllTypesMatch<["res", "src"]>], 1>,`
`193`	`193`	`Arguments<(ins LLVM_Type:$src)> {`
`194`	`194`	`let results = (outs LLVM_Type:$res);`
`195`	`195`	`let summary = "Get the value in first active lane.";`