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[RDF] Rename RegisterId field in RegisterRef Reg->Id. NFC (#168154)
Not all RegisterId values are registers, so Id is a more appropriate name. Use asMCReg() in some places that assumed it was a register.
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+77
-77
lines changed

7 files changed

+77
-77
lines changed

‎llvm/include/llvm/CodeGen/RDFGraph.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -462,7 +462,7 @@ struct TargetOperandInfo {
462462

463463
// Packed register reference. Only used for storage.
464464
struct PackedRegisterRef {
465-
RegisterId Reg;
465+
RegisterId Id;
466466
uint32_t MaskId;
467467
};
468468

@@ -779,13 +779,13 @@ struct DataFlowGraph {
779779
void releaseBlock(NodeId B, DefStackMap &DefM);
780780

781781
PackedRegisterRef pack(RegisterRef RR) {
782-
return {RR.Reg, LMI.getIndexForLaneMask(RR.Mask)};
782+
return {RR.Id, LMI.getIndexForLaneMask(RR.Mask)};
783783
}
784784
PackedRegisterRef pack(RegisterRef RR) const {
785-
return {RR.Reg, LMI.getIndexForLaneMask(RR.Mask)};
785+
return {RR.Id, LMI.getIndexForLaneMask(RR.Mask)};
786786
}
787787
RegisterRef unpack(PackedRegisterRef PR) const {
788-
return RegisterRef(PR.Reg, LMI.getLaneMaskForIndex(PR.MaskId));
788+
return RegisterRef(PR.Id, LMI.getLaneMaskForIndex(PR.MaskId));
789789
}
790790

791791
RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const;

‎llvm/include/llvm/CodeGen/RDFRegisters.h‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -91,45 +91,45 @@ struct RegisterRef {
9191
static constexpr RegisterId UnitFlag = 1u << 31;
9292

9393
public:
94-
RegisterId Reg = 0;
94+
RegisterId Id = 0;
9595
LaneBitmask Mask = LaneBitmask::getNone(); // Only for registers.
9696

9797
constexpr RegisterRef() = default;
9898
constexpr explicit RegisterRef(RegisterId R,
9999
LaneBitmask M = LaneBitmask::getAll())
100-
: Reg(R), Mask(isRegId(R) && R != 0 ? M : LaneBitmask::getNone()) {}
100+
: Id(R), Mask(isRegId(R) && R != 0 ? M : LaneBitmask::getNone()) {}
101101

102102
// Classify null register as a "register".
103-
constexpr bool isReg() const { return Reg == 0 || isRegId(Reg); }
104-
constexpr bool isUnit() const { return isUnitId(Reg); }
105-
constexpr bool isMask() const { return isMaskId(Reg); }
103+
constexpr bool isReg() const { return Id == 0 || isRegId(Id); }
104+
constexpr bool isUnit() const { return isUnitId(Id); }
105+
constexpr bool isMask() const { return isMaskId(Id); }
106106

107107
constexpr MCRegister asMCReg() const {
108108
assert(isReg());
109-
return Reg;
109+
return Id;
110110
}
111111

112112
constexpr MCRegUnit asMCRegUnit() const {
113113
assert(isUnit());
114-
return Reg & ~UnitFlag;
114+
return Id & ~UnitFlag;
115115
}
116116

117117
constexpr unsigned asMaskIdx() const {
118118
assert(isMask());
119-
return Reg & ~MaskFlag;
119+
return Id & ~MaskFlag;
120120
}
121121

122-
constexpr operator bool() const {
123-
return !isReg() || (Reg != 0 && Mask.any());
122+
explicit constexpr operator bool() const {
123+
return !isReg() || (Id != 0 && Mask.any());
124124
}
125125

126126
size_t hash() const {
127-
return std::hash<RegisterId>{}(Reg) ^
127+
return std::hash<RegisterId>{}(Id) ^
128128
std::hash<LaneBitmask::Type>{}(Mask.getAsInteger());
129129
}
130130

131131
static constexpr bool isRegId(RegisterId Id) {
132-
return !(Id & UnitFlag) && !(Id & MaskFlag);
132+
return Id != 0 && !(Id & UnitFlag) && !(Id & MaskFlag);
133133
}
134134
static constexpr bool isUnitId(RegisterId Id) { return Id & UnitFlag; }
135135
static constexpr bool isMaskId(RegisterId Id) { return Id & MaskFlag; }
@@ -151,21 +151,21 @@ struct PhysicalRegisterInfo {
151151
return RegisterRef::toMaskId(RegMasks.find(RM));
152152
}
153153

154-
const uint32_t *getRegMaskBits(RegisterId R) const {
155-
return RegMasks.get(RegisterRef(R).asMaskIdx());
154+
const uint32_t *getRegMaskBits(RegisterRef RR) const {
155+
return RegMasks.get(RR.asMaskIdx());
156156
}
157157

158158
bool alias(RegisterRef RA, RegisterRef RB) const;
159159

160160
// Returns the set of aliased physical registers.
161-
std::set<RegisterId> getAliasSet(RegisterId Reg) const;
161+
std::set<RegisterId> getAliasSet(RegisterRef RR) const;
162162

163163
RegisterRef getRefForUnit(uint32_t U) const {
164164
return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
165165
}
166166

167-
const BitVector &getMaskUnits(RegisterId MaskId) const {
168-
return MaskInfos[RegisterRef(MaskId).asMaskIdx()].Units;
167+
const BitVector &getMaskUnits(RegisterRef RR) const {
168+
return MaskInfos[RR.asMaskIdx()].Units;
169169
}
170170

171171
std::set<RegisterId> getUnits(RegisterRef RR) const;

‎llvm/lib/CodeGen/RDFGraph.cpp‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1061,13 +1061,13 @@ void DataFlowGraph::pushClobbers(Instr IA, DefStackMap &DefM) {
10611061

10621062
// Push the definition on the stack for the register and all aliases.
10631063
// The def stack traversal in linkNodeUp will check the exact aliasing.
1064-
DefM[RR.Reg].push(DA);
1065-
Defined.insert(RR.Reg);
1066-
for (RegisterId A : getPRI().getAliasSet(RR.Reg)) {
1064+
DefM[RR.Id].push(DA);
1065+
Defined.insert(RR.Id);
1066+
for (RegisterId A : getPRI().getAliasSet(RR)) {
10671067
if (RegisterRef::isRegId(A) && !isTracked(RegisterRef(A)))
10681068
continue;
10691069
// Check that we don't push the same def twice.
1070-
assert(A != RR.Reg);
1070+
assert(A != RR.Id);
10711071
if (!Defined.count(A))
10721072
DefM[A].push(DA);
10731073
}
@@ -1109,7 +1109,7 @@ void DataFlowGraph::pushDefs(Instr IA, DefStackMap &DefM) {
11091109
#ifndef NDEBUG
11101110
// Assert if the register is defined in two or more unrelated defs.
11111111
// This could happen if there are two or more def operands defining it.
1112-
if (!Defined.insert(RR.Reg).second) {
1112+
if (!Defined.insert(RR.Id).second) {
11131113
MachineInstr *MI = Stmt(IA).Addr->getCode();
11141114
dbgs() << "Multiple definitions of register: " << Print(RR, *this)
11151115
<< " in\n " << *MI << "in " << printMBBReference(*MI->getParent())
@@ -1119,12 +1119,12 @@ void DataFlowGraph::pushDefs(Instr IA, DefStackMap &DefM) {
11191119
#endif
11201120
// Push the definition on the stack for the register and all aliases.
11211121
// The def stack traversal in linkNodeUp will check the exact aliasing.
1122-
DefM[RR.Reg].push(DA);
1123-
for (RegisterId A : getPRI().getAliasSet(RR.Reg)) {
1122+
DefM[RR.Id].push(DA);
1123+
for (RegisterId A : getPRI().getAliasSet(RR)) {
11241124
if (RegisterRef::isRegId(A) && !isTracked(RegisterRef(A)))
11251125
continue;
11261126
// Check that we don't push the same def twice.
1127-
assert(A != RR.Reg);
1127+
assert(A != RR.Id);
11281128
DefM[A].push(DA);
11291129
}
11301130
// Mark all the related defs as visited.
@@ -1465,11 +1465,11 @@ void DataFlowGraph::buildPhis(BlockRefsMap &PhiM, Block BA,
14651465

14661466
for (RegisterRef RR : Defs.refs()) {
14671467
if (!DefM.empty()) {
1468-
auto F = DefM.find(RR.Reg);
1468+
auto F = DefM.find(RR.Id);
14691469
// Do not create a phi for unallocatable registers, or for registers
14701470
// that are never livein to BA.
14711471
// If a phi exists for RR, do not create another.
1472-
if (!MRI.isAllocatable(RR.Reg) || PhiDefs.hasCoverOf(RR) ||
1472+
if (!MRI.isAllocatable(RR.asMCReg()) || PhiDefs.hasCoverOf(RR) ||
14731473
F == DefM.end() || F->second.empty())
14741474
continue;
14751475
// Do not create a phi, if all reaching defs are clobbering
@@ -1601,7 +1601,7 @@ void DataFlowGraph::linkStmtRefs(DefStackMap &DefM, Stmt SA, Predicate P) {
16011601
Defs.insert(RR);
16021602
#endif
16031603

1604-
auto F = DefM.find(RR.Reg);
1604+
auto F = DefM.find(RR.Id);
16051605
if (F == DefM.end())
16061606
continue;
16071607
DefStack &DS = F->second;
@@ -1691,7 +1691,7 @@ void DataFlowGraph::linkBlockRefs(DefStackMap &DefM, BlockRefsMap &PhiClobberM,
16911691
for (auto U : IA.Addr->members_if(IsUseForBA, *this)) {
16921692
PhiUse PUA = U;
16931693
RegisterRef RR = PUA.Addr->getRegRef(*this);
1694-
linkRefUp<UseNode *>(IA, PUA, DefM[RR.Reg]);
1694+
linkRefUp<UseNode *>(IA, PUA, DefM[RR.Id]);
16951695
}
16961696
}
16971697
}

‎llvm/lib/CodeGen/RDFLiveness.cpp‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -511,7 +511,7 @@ void Liveness::computePhiInfo() {
511511
uint16_t F = A.Addr->getFlags();
512512
if ((F & (NodeAttrs::Undef | NodeAttrs::PhiRef)) == 0) {
513513
RegisterRef R = A.Addr->getRegRef(DFG);
514-
RealUses[R.Reg].insert({A.Id, R.Mask});
514+
RealUses[R.Id].insert({A.Id, R.Mask});
515515
}
516516
UN = A.Addr->getSibling();
517517
}
@@ -706,8 +706,8 @@ void Liveness::computePhiInfo() {
706706
LaneBitmask M = R.Mask & V.second;
707707
if (M.none())
708708
continue;
709-
if (RegisterRef SS = ClearIn(RegisterRef(R.Reg, M), MidDefs, SM)) {
710-
NodeRefSet &RS = RealUseMap[P.first][SS.Reg];
709+
if (RegisterRef SS = ClearIn(RegisterRef(R.Id, M), MidDefs, SM)) {
710+
NodeRefSet &RS = RealUseMap[P.first][SS.Id];
711711
Changed |= RS.insert({V.first, SS.Mask}).second;
712712
}
713713
}
@@ -839,7 +839,7 @@ void Liveness::computeLiveIns() {
839839
RegisterAggr TA(PRI);
840840
TA.insert(D.Addr->getRegRef(DFG)).intersect(S);
841841
LaneBitmask TM = TA.makeRegRef().Mask;
842-
LOX[S.Reg].insert({D.Id, TM});
842+
LOX[S.Id].insert({D.Id, TM});
843843
}
844844
}
845845
}
@@ -899,7 +899,7 @@ void Liveness::resetLiveIns() {
899899
// Add the newly computed live-ins.
900900
const RegisterAggr &LiveIns = LiveMap[&B];
901901
for (RegisterRef R : LiveIns.refs())
902-
B.addLiveIn({MCPhysReg(R.Reg), R.Mask});
902+
B.addLiveIn({R.asMCReg(), R.Mask});
903903
}
904904
}
905905

@@ -1046,7 +1046,7 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
10461046

10471047
for (const std::pair<const RegisterId, NodeRefSet> &LE : LiveInCopy) {
10481048
RegisterRef LRef(LE.first);
1049-
NodeRefSet &NewDefs = LiveIn[LRef.Reg]; // To be filled.
1049+
NodeRefSet &NewDefs = LiveIn[LRef.Id]; // To be filled.
10501050
const NodeRefSet &OldDefs = LE.second;
10511051
for (NodeRef OR : OldDefs) {
10521052
// R is a def node that was live-on-exit
@@ -1129,7 +1129,7 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
11291129
RegisterRef RR = UA.Addr->getRegRef(DFG);
11301130
for (NodeAddr<DefNode *> D : getAllReachingDefs(UA))
11311131
if (getBlockWithRef(D.Id) != B)
1132-
LiveIn[RR.Reg].insert({D.Id, RR.Mask});
1132+
LiveIn[RR.Id].insert({D.Id, RR.Mask});
11331133
}
11341134
}
11351135

‎llvm/lib/CodeGen/RDFRegisters.cpp‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -101,13 +101,13 @@ bool PhysicalRegisterInfo::alias(RegisterRef RA, RegisterRef RB) const {
101101
return !disjoint(getUnits(RA), getUnits(RB));
102102
}
103103

104-
std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const {
104+
std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterRef RR) const {
105105
// Do not include Reg in the alias set.
106106
std::set<RegisterId> AS;
107-
assert(!RegisterRef::isUnitId(Reg) && "No units allowed");
108-
if (RegisterRef::isMaskId(Reg)) {
107+
assert(!RR.isUnit() && "No units allowed");
108+
if (RR.isMask()) {
109109
// XXX SLOW
110-
const uint32_t *MB = getRegMaskBits(Reg);
110+
const uint32_t *MB = getRegMaskBits(RR);
111111
for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) {
112112
if (MB[i / 32] & (1u << (i % 32)))
113113
continue;
@@ -116,8 +116,8 @@ std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const {
116116
return AS;
117117
}
118118

119-
assert(RegisterRef::isRegId(Reg));
120-
for (MCRegAliasIterator AI(Reg, &TRI, false); AI.isValid(); ++AI)
119+
assert(RR.isReg());
120+
for (MCRegAliasIterator AI(RR.asMCReg(), &TRI, false); AI.isValid(); ++AI)
121121
AS.insert(*AI);
122122

123123
return AS;
@@ -139,7 +139,7 @@ std::set<RegisterId> PhysicalRegisterInfo::getUnits(RegisterRef RR) const {
139139

140140
assert(RR.isMask());
141141
unsigned NumRegs = TRI.getNumRegs();
142-
const uint32_t *MB = getRegMaskBits(RR.Reg);
142+
const uint32_t *MB = getRegMaskBits(RR);
143143
for (unsigned I = 0, E = (NumRegs + 31) / 32; I != E; ++I) {
144144
uint32_t C = ~MB[I]; // Clobbered regs
145145
if (I == 0) // Reg 0 should be ignored
@@ -160,7 +160,7 @@ std::set<RegisterId> PhysicalRegisterInfo::getUnits(RegisterRef RR) const {
160160
}
161161

162162
RegisterRef PhysicalRegisterInfo::mapTo(RegisterRef RR, RegisterId R) const {
163-
if (RR.Reg == R)
163+
if (RR.Id == R)
164164
return RR;
165165
if (unsigned Idx = TRI.getSubRegIndex(RegisterRef(R).asMCReg(), RR.asMCReg()))
166166
return RegisterRef(R, TRI.composeSubRegIndexLaneMask(Idx, RR.Mask));
@@ -177,11 +177,11 @@ RegisterRef PhysicalRegisterInfo::mapTo(RegisterRef RR, RegisterId R) const {
177177

178178
bool PhysicalRegisterInfo::equal_to(RegisterRef A, RegisterRef B) const {
179179
if (!A.isReg() || !B.isReg()) {
180-
// For non-regs, or comparing reg and non-reg, use only the Reg member.
181-
return A.Reg == B.Reg;
180+
// For non-regs, or comparing reg and non-reg, use only the Id member.
181+
return A.Id == B.Id;
182182
}
183183

184-
if (A.Reg == B.Reg)
184+
if (A.Id == B.Id)
185185
return A.Mask == B.Mask;
186186

187187
// Compare reg units lexicographically.
@@ -213,14 +213,14 @@ bool PhysicalRegisterInfo::equal_to(RegisterRef A, RegisterRef B) const {
213213

214214
bool PhysicalRegisterInfo::less(RegisterRef A, RegisterRef B) const {
215215
if (!A.isReg() || !B.isReg()) {
216-
// For non-regs, or comparing reg and non-reg, use only the Reg member.
217-
return A.Reg < B.Reg;
216+
// For non-regs, or comparing reg and non-reg, use only the Id member.
217+
return A.Id < B.Id;
218218
}
219219

220-
if (A.Reg == B.Reg)
220+
if (A.Id == B.Id)
221221
return A.Mask < B.Mask;
222222
if (A.Mask == B.Mask)
223-
return A.Reg < B.Reg;
223+
return A.Id < B.Id;
224224

225225
// Compare reg units lexicographically.
226226
llvm::MCRegUnitMaskIterator AI(A.asMCReg(), &getTRI());
@@ -275,7 +275,7 @@ void PhysicalRegisterInfo::print(raw_ostream &OS, const RegisterAggr &A) const {
275275

276276
bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
277277
if (RR.isMask())
278-
return Units.anyCommon(PRI.getMaskUnits(RR.Reg));
278+
return Units.anyCommon(PRI.getMaskUnits(RR));
279279

280280
for (MCRegUnitMaskIterator U(RR.asMCReg(), &PRI.getTRI()); U.isValid(); ++U) {
281281
auto [Unit, LaneMask] = *U;
@@ -288,7 +288,7 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
288288

289289
bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
290290
if (RR.isMask()) {
291-
BitVector T(PRI.getMaskUnits(RR.Reg));
291+
BitVector T(PRI.getMaskUnits(RR));
292292
return T.reset(Units).none();
293293
}
294294

@@ -303,7 +303,7 @@ bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
303303

304304
RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
305305
if (RR.isMask()) {
306-
Units |= PRI.getMaskUnits(RR.Reg);
306+
Units |= PRI.getMaskUnits(RR);
307307
return *this;
308308
}
309309

@@ -392,7 +392,7 @@ RegisterAggr::ref_iterator::ref_iterator(const RegisterAggr &RG, bool End)
392392
: Owner(&RG) {
393393
for (int U = RG.Units.find_first(); U >= 0; U = RG.Units.find_next(U)) {
394394
RegisterRef R = RG.PRI.getRefForUnit(U);
395-
Masks[R.Reg] |= R.Mask;
395+
Masks[R.Id] |= R.Mask;
396396
}
397397
Pos = End ? Masks.end() : Masks.begin();
398398
Index = End ? Masks.size() : 0;

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