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1 | | -// RUN: mlir-translate -no-implicit-module -split-input-file -test-spirv-roundtrip %s | FileCheck %s |
| 1 | +// RUN: mlir-translate -no-implicit-module -split-input-file -test-spirv-roundtrip -verify-diagnostics %s | FileCheck %s |
2 | 2 |
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3 | 3 | spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], []> { |
4 | 4 | // CHECK: location = 0 : i32 |
@@ -113,11 +113,41 @@ spirv.func @fp_rounding_mode(%arg: f32) -> f16 "None" { |
113 | 113 | // CHECK-LABEL: spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [CacheControlsINTEL], [SPV_INTEL_cache_controls]> { |
114 | 114 |
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115 | 115 | spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [CacheControlsINTEL], [SPV_INTEL_cache_controls]> { |
116 | | - spirv.func @foo() "None" { |
| 116 | + spirv.func @cache_controls() "None" { |
117 | 117 | // CHECK: spirv.Variable {cache_control_load_intel = [#spirv.cache_control_load_intel<cache_level = 0, load_cache_control = Uncached>, #spirv.cache_control_load_intel<cache_level = 1, load_cache_control = Cached>, #spirv.cache_control_load_intel<cache_level = 2, load_cache_control = InvalidateAfterR>]} : !spirv.ptr<f32, Function> |
118 | 118 | %0 = spirv.Variable {cache_control_load_intel = [#spirv.cache_control_load_intel<cache_level = 0, load_cache_control = Uncached>, #spirv.cache_control_load_intel<cache_level = 1, load_cache_control = Cached>, #spirv.cache_control_load_intel<cache_level = 2, load_cache_control = InvalidateAfterR>]} : !spirv.ptr<f32, Function> |
119 | 119 | // CHECK: spirv.Variable {cache_control_store_intel = [#spirv.cache_control_store_intel<cache_level = 0, store_cache_control = Uncached>, #spirv.cache_control_store_intel<cache_level = 1, store_cache_control = WriteThrough>, #spirv.cache_control_store_intel<cache_level = 2, store_cache_control = WriteBack>]} : !spirv.ptr<f32, Function> |
120 | 120 | %1 = spirv.Variable {cache_control_store_intel = [#spirv.cache_control_store_intel<cache_level = 0, store_cache_control = Uncached>, #spirv.cache_control_store_intel<cache_level = 1, store_cache_control = WriteThrough>, #spirv.cache_control_store_intel<cache_level = 2, store_cache_control = WriteBack>]} : !spirv.ptr<f32, Function> |
121 | 121 | spirv.Return |
122 | 122 | } |
123 | 123 | } |
| 124 | + |
| 125 | +// ----- |
| 126 | + |
| 127 | +spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [CacheControlsINTEL], [SPV_INTEL_cache_controls]> { |
| 128 | + spirv.func @cache_controls_invalid_type() "None" { |
| 129 | + // expected-error@below {{expecting array attribute of CacheControlLoadINTEL for CacheControlLoadINTEL}} |
| 130 | + %0 = spirv.Variable {cache_control_load_intel = #spirv.cache_control_load_intel<cache_level = 0, load_cache_control = Uncached>} : !spirv.ptr<f32, Function> |
| 131 | + spirv.Return |
| 132 | + } |
| 133 | +} |
| 134 | + |
| 135 | +// ----- |
| 136 | + |
| 137 | +spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [CacheControlsINTEL], [SPV_INTEL_cache_controls]> { |
| 138 | + spirv.func @cache_controls_invalid_type() "None" { |
| 139 | + // expected-error@below {{expecting array attribute of CacheControlStoreINTEL for CacheControlStoreINTEL}} |
| 140 | + %0 = spirv.Variable {cache_control_store_intel = [#spirv.cache_control_store_intel<cache_level = 0, store_cache_control = Uncached>, 0 : i32]} : !spirv.ptr<f32, Function> |
| 141 | + spirv.Return |
| 142 | + } |
| 143 | +} |
| 144 | + |
| 145 | +// ----- |
| 146 | + |
| 147 | +spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [CacheControlsINTEL], [SPV_INTEL_cache_controls]> { |
| 148 | + spirv.func @cache_controls_invalid_type() "None" { |
| 149 | + // expected-error@below {{expecting non-empty array attribute of CacheControlStoreINTEL for CacheControlStoreINTEL}} |
| 150 | + %0 = spirv.Variable {cache_control_store_intel = []} : !spirv.ptr<f32, Function> |
| 151 | + spirv.Return |
| 152 | + } |
| 153 | +} |
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