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[X86][NFC] Hoist out N->getOpcode() used in ReplaceNodeResults
Address comment from https://github.com/llvm/llvm-project/pull/119391/files#r1878388699
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‎llvm/lib/Target/X86/X86ISelLowering.cpp‎

Lines changed: 18 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -33259,7 +33259,8 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3325933259
SmallVectorImpl<SDValue>&Results,
3326033260
SelectionDAG &DAG) const {
3326133261
SDLoc dl(N);
33262-
switch (N->getOpcode()) {
33262+
unsigned Opc = N->getOpcode();
33263+
switch (Opc) {
3326333264
default:
3326433265
#ifndef NDEBUG
3326533266
dbgs() << "ReplaceNodeResults: ";
@@ -33355,7 +33356,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3335533356
EVT VT = N->getValueType(0);
3335633357
assert(getTypeAction(*DAG.getContext(), VT) == TypeWidenVector &&
3335733358
VT == MVT::v2i32 && "Unexpected VT!");
33358-
bool IsSigned = N->getOpcode() == ISD::SMULO;
33359+
bool IsSigned = Opc == ISD::SMULO;
3335933360
unsigned ExtOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3336033361
SDValue Op0 = DAG.getNode(ExtOpc, dl, MVT::v2i64, N->getOperand(0));
3336133362
SDValue Op1 = DAG.getNode(ExtOpc, dl, MVT::v2i64, N->getOperand(1));
@@ -33412,7 +33413,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3341233413
Ops[0] = N->getOperand(1);
3341333414
SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWideVT, Ops);
3341433415

33415-
SDValue Res = DAG.getNode(N->getOpcode(), dl, WideVT, InVec0, InVec1);
33416+
SDValue Res = DAG.getNode(Opc, dl, WideVT, InVec0, InVec1);
3341633417
Results.push_back(Res);
3341733418
return;
3341833419
}
@@ -33450,7 +33451,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3345033451
EVT ResVT = getTypeToTransformTo(*DAG.getContext(), VT);
3345133452
SDValue N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Ops0);
3345233453
SDValue N1 = DAG.getConstant(SplatVal, dl, ResVT);
33453-
SDValue Res = DAG.getNode(N->getOpcode(), dl, ResVT, N0, N1);
33454+
SDValue Res = DAG.getNode(Opc, dl, ResVT, N0, N1);
3345433455
Results.push_back(Res);
3345533456
}
3345633457
return;
@@ -33571,7 +33572,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3357133572
(InVT == MVT::v4i16 || InVT == MVT::v4i8)){
3357233573
assert(getTypeAction(*DAG.getContext(), InVT) == TypeWidenVector &&
3357333574
"Unexpected type action!");
33574-
assert(N->getOpcode() == ISD::SIGN_EXTEND && "Unexpected opcode");
33575+
assert(Opc == ISD::SIGN_EXTEND && "Unexpected opcode");
3357533576
// Custom split this so we can extend i8/i16->i32 invec. This is better
3357633577
// since sign_extend_inreg i8/i16->i64 requires an extend to i32 using
3357733578
// sra. Then extending from i32 to i64 using pcmpgt. By custom splitting
@@ -33608,7 +33609,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3360833609

3360933610
// Promote the input to 128 bits. Type legalization will turn this into
3361033611
// zext_inreg/sext_inreg.
33611-
In = DAG.getNode(N->getOpcode(), dl, InVT, In);
33612+
In = DAG.getNode(Opc, dl, InVT, In);
3361233613
}
3361333614

3361433615
// Perform custom splitting instead of the two stage extend we would get
@@ -33617,7 +33618,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3361733618
std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
3361833619
assert(isTypeLegal(LoVT) && "Split VT not legal?");
3361933620

33620-
SDValue Lo = getEXTEND_VECTOR_INREG(N->getOpcode(), dl, LoVT, In, DAG);
33621+
SDValue Lo = getEXTEND_VECTOR_INREG(Opc, dl, LoVT, In, DAG);
3362133622

3362233623
// We need to shift the input over by half the number of elements.
3362333624
unsigned NumElts = InVT.getVectorNumElements();
@@ -33627,7 +33628,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3362733628
ShufMask[i] = i + HalfNumElts;
3362833629

3362933630
SDValue Hi = DAG.getVectorShuffle(InVT, dl, In, In, ShufMask);
33630-
Hi = getEXTEND_VECTOR_INREG(N->getOpcode(), dl, HiVT, Hi, DAG);
33631+
Hi = getEXTEND_VECTOR_INREG(Opc, dl, HiVT, Hi, DAG);
3363133632

3363233633
SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
3363333634
Results.push_back(Res);
@@ -33639,8 +33640,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3363933640
case ISD::FP_TO_UINT:
3364033641
case ISD::STRICT_FP_TO_UINT: {
3364133642
bool IsStrict = N->isStrictFPOpcode();
33642-
bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT ||
33643-
N->getOpcode() == ISD::STRICT_FP_TO_SINT;
33643+
bool IsSigned = Opc == ISD::FP_TO_SINT || Opc == ISD::STRICT_FP_TO_SINT;
3364433644
EVT VT = N->getValueType(0);
3364533645
SDValue Src = N->getOperand(IsStrict ? 1 : 0);
3364633646
SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
@@ -33651,13 +33651,13 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3365133651
EVT NVT = VT.isVector() ? VT.changeVectorElementType(MVT::f32) : MVT::f32;
3365233652
if (IsStrict) {
3365333653
Res =
33654-
DAG.getNode(N->getOpcode(), dl, {VT, MVT::Other},
33654+
DAG.getNode(Opc, dl, {VT, MVT::Other},
3365533655
{Chain, DAG.getNode(ISD::STRICT_FP_EXTEND, dl,
3365633656
{NVT, MVT::Other}, {Chain, Src})});
3365733657
Chain = Res.getValue(1);
3365833658
} else {
33659-
Res = DAG.getNode(N->getOpcode(), dl, VT,
33660-
DAG.getNode(ISD::FP_EXTEND, dl, NVT, Src));
33659+
Res =
33660+
DAG.getNode(Opc, dl, VT, DAG.getNode(ISD::FP_EXTEND, dl, NVT, Src));
3366133661
}
3366233662
Results.push_back(Res);
3366333663
if (IsStrict)
@@ -33680,13 +33680,12 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3368033680
}
3368133681

3368233682
if (IsStrict) {
33683-
unsigned Opc =
33684-
IsSigned ? X86ISD::STRICT_CVTTP2SI : X86ISD::STRICT_CVTTP2UI;
33683+
Opc = IsSigned ? X86ISD::STRICT_CVTTP2SI : X86ISD::STRICT_CVTTP2UI;
3368533684
Res =
3368633685
DAG.getNode(Opc, dl, {ResVT, MVT::Other}, {N->getOperand(0), Src});
3368733686
Chain = Res.getValue(1);
3368833687
} else {
33689-
unsigned Opc = IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI;
33688+
Opc = IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI;
3369033689
Res = DAG.getNode(Opc, dl, ResVT, Src);
3369133690
}
3369233691

@@ -33772,7 +33771,6 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3377233771
return;
3377333772
}
3377433773

33775-
unsigned Opc;
3377633774
if (IsStrict)
3377733775
Opc = IsSigned ? X86ISD::STRICT_CVTTP2SI : X86ISD::STRICT_CVTTP2UI;
3377833776
else
@@ -33811,7 +33809,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3381133809
if (Src.getValueType() == MVT::v2f32 && IsStrict) {
3381233810
Src = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32, Src,
3381333811
DAG.getConstantFP(0.0, dl, MVT::v2f32));
33814-
SDValue Res = DAG.getNode(N->getOpcode(), dl, {MVT::v4i32, MVT::Other},
33812+
SDValue Res = DAG.getNode(Opc, dl, {MVT::v4i32, MVT::Other},
3381533813
{N->getOperand(0), Src});
3381633814
Results.push_back(Res);
3381733815
Results.push_back(Res.getValue(1));
@@ -33835,7 +33833,6 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3383533833
std::max(NumElts, 128U / (unsigned)SrcVT.getSizeInBits());
3383633834
MVT VecVT = MVT::getVectorVT(MVT::i64, NumElts);
3383733835
MVT VecInVT = MVT::getVectorVT(SrcVT.getSimpleVT(), SrcElts);
33838-
unsigned Opc = N->getOpcode();
3383933836
if (NumElts != SrcElts) {
3384033837
if (IsStrict)
3384133838
Opc = IsSigned ? X86ISD::STRICT_CVTTP2SI : X86ISD::STRICT_CVTTP2UI;
@@ -33889,8 +33886,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3388933886
case ISD::UINT_TO_FP:
3389033887
case ISD::STRICT_UINT_TO_FP: {
3389133888
bool IsStrict = N->isStrictFPOpcode();
33892-
bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP ||
33893-
N->getOpcode() == ISD::STRICT_SINT_TO_FP;
33889+
bool IsSigned = Opc == ISD::SINT_TO_FP || Opc == ISD::STRICT_SINT_TO_FP;
3389433890
EVT VT = N->getValueType(0);
3389533891
SDValue Src = N->getOperand(IsStrict ? 1 : 0);
3389633892
if (VT.getVectorElementType() == MVT::f16 && Subtarget.hasFP16() &&
@@ -33984,7 +33980,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3398433980
// FIXME: Should generic type legalizer do this?
3398533981
Src = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
3398633982
DAG.getConstant(0, dl, MVT::v2i32));
33987-
SDValue Res = DAG.getNode(N->getOpcode(), dl, {MVT::v4f32, MVT::Other},
33983+
SDValue Res = DAG.getNode(Opc, dl, {MVT::v4f32, MVT::Other},
3398833984
{N->getOperand(0), Src});
3398933985
Results.push_back(Res);
3399033986
Results.push_back(Res.getValue(1));

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