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fixup! capitalize variable name
1 parent 61e2023 commit 550489b

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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7769,7 +7769,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, StoredVal,
77707770
DAG.getTargetConstant(1, DL, MVT::i32));
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7772-
return DAG.getMemIntrinsicNode(
7772+
return DAG.getMemIntrinsicNode(
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RISCVISD::SD_RV32, DL, DAG.getVTList(MVT::Other),
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{Store->getChain(), Lo, Hi, Store->getBasePtr()}, MVT::i64,
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Store->getMemOperand());
@@ -13746,14 +13746,14 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
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if (!Subtarget.enableUnalignedScalarMem() && Ld->getAlign() < 8)
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return;
1374813748

13749-
SDLoc dl(N);
13749+
SDLoc DL(N);
1375013750
SDValue Result = DAG.getMemIntrinsicNode(
13751-
RISCVISD::LD_RV32, dl,
13751+
RISCVISD::LD_RV32, DL,
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DAG.getVTList({MVT::i32, MVT::i32, MVT::Other}),
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{Ld->getChain(), Ld->getBasePtr()}, MVT::i64, Ld->getMemOperand());
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SDValue Lo = Result.getValue(0);
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SDValue Hi = Result.getValue(1);
13756-
SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
13756+
SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
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Results.append({Pair, Result.getValue(2)});
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return;
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}

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